mirror of https://github.com/VLSIDA/OpenRAM.git
107 lines
4.2 KiB
Python
107 lines
4.2 KiB
Python
# See LICENSE for licensing information.
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#
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#Copyright (c) 2016-2019 Regents of the University of California and The Board
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#of Regents for the Oklahoma Agricultural and Mechanical College
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#(acting for and on behalf of Oklahoma State University)
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#All rights reserved.
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#
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import design
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import debug
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import utils
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from tech import GDS,layer,parameter,drc
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import logical_effort
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class bitcell(design.design):
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"""
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A single bit cell (6T, 8T, etc.) This module implements the
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single memory cell used in the design. It is a hand-made cell, so
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the layout and netlist should be available in the technology
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library.
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"""
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pin_names = ["bl", "br", "wl", "vdd", "gnd"]
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internal_nets = ['Q', 'Qbar']
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type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
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(width,height) = utils.get_libcell_size("cell_6t", GDS["unit"], layer["boundary"])
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pin_map = utils.get_libcell_pins(pin_names, "cell_6t", GDS["unit"])
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def __init__(self, name=""):
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# Ignore the name argument
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design.design.__init__(self, "cell_6t")
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debug.info(2, "Create bitcell")
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self.width = bitcell.width
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self.height = bitcell.height
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self.pin_map = bitcell.pin_map
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self.add_pin_types(self.type_list)
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self.nets_match = self.check_internal_nets()
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def analytical_delay(self, corner, slew, load=0, swing = 0.5):
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parasitic_delay = 1
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size = 0.5 #This accounts for bitline being drained thought the access TX and internal node
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cin = 3 #Assumes always a minimum sizes inverter. Could be specified in the tech.py file.
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return logical_effort.logical_effort('bitline', size, cin, load, parasitic_delay, False)
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def list_bitcell_pins(self, col, row):
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""" Creates a list of connections in the bitcell, indexed by column and row, for instance use in bitcell_array """
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bitcell_pins = ["bl_{0}".format(col),
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"br_{0}".format(col),
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"wl_{0}".format(row),
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"vdd",
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"gnd"]
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return bitcell_pins
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def list_all_wl_names(self):
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""" Creates a list of all wordline pin names """
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row_pins = ["wl"]
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return row_pins
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def list_all_bitline_names(self):
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""" Creates a list of all bitline pin names (both bl and br) """
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column_pins = ["bl", "br"]
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return column_pins
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def list_all_bl_names(self):
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""" Creates a list of all bl pins names """
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column_pins = ["bl"]
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return column_pins
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def list_all_br_names(self):
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""" Creates a list of all br pins names """
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column_pins = ["br"]
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return column_pins
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def analytical_power(self, corner, load):
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"""Bitcell power in nW. Only characterizes leakage."""
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from tech import spice
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leakage = spice["bitcell_leakage"]
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dynamic = 0 #temporary
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total_power = self.return_power(dynamic, leakage)
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return total_power
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def check_internal_nets(self):
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"""For handmade cell, checks sp file contains the storage nodes."""
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nets_match = True
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for net in self.internal_nets:
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nets_match = nets_match and self.check_net_in_spice(net)
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return nets_match
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def get_storage_net_names(self):
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"""Returns names of storage nodes in bitcell in [non-inverting, inverting] format."""
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#Checks that they do exist
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if self.nets_match:
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return self.internal_nets
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else:
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debug.info(1,"Storage nodes={} not found in spice file.".format(self.internal_nets))
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return None
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def get_wl_cin(self):
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"""Return the relative capacitance of the access transistor gates"""
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#This is a handmade cell so the value must be entered in the tech.py file or estimated.
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#Calculated in the tech file by summing the widths of all the related gates and dividing by the minimum width.
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access_tx_cin = parameter["6T_access_size"]/drc["minwidth_tx"]
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return 2*access_tx_cin
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def build_graph(self, graph, inst_name, port_nets):
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"""Adds edges based on inputs/outputs. Overrides base class function."""
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self.add_graph_edges(graph, port_nets) |