mirror of https://github.com/VLSIDA/OpenRAM.git
190 lines
6.8 KiB
Python
190 lines
6.8 KiB
Python
import debug
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import design
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from tech import drc
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from math import log
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from vector import vector
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from globals import OPTS
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from pinv import pinv
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class pinvbuf(design.design):
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"""
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This is a simple inverter/buffer used for driving loads. It is
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used in the column decoder for 1:2 decoding and as the clock buffer.
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"""
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unique_id = 1
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def __init__(self, driver_size=4, height=None, name=""):
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self.stage_effort = 4
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self.row_height = height
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# FIXME: Change the number of stages to support high drives.
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# stage effort of 4 or less
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# The pinvbuf has a FO of 2 for the first stage, so the second stage
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# should be sized "half" to prevent loading of the first stage
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self.driver_size = driver_size
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self.predriver_size = max(int(self.driver_size/(self.stage_effort/2)),1)
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if name=="":
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name = "pinvbuf_{0}_{1}_{2}".format(self.predriver_size, self.driver_size, pinvbuf.unique_id)
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pinvbuf.unique_id += 1
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design.design.__init__(self, name)
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debug.info(1, "Creating {}".format(self.name))
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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self.add_pins()
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self.add_modules()
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self.create_insts()
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def create_layout(self):
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self.width = 2*self.inv1.width + self.inv2.width
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self.height = 2*self.inv1.height
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self.place_modules()
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self.route_wires()
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self.add_layout_pins()
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self.offset_all_coordinates()
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self.DRC_LVS()
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def add_pins(self):
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self.add_pin("A")
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self.add_pin("Zb")
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self.add_pin("Z")
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self.add_pin("vdd")
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self.add_pin("gnd")
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def add_modules(self):
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# Shield the cap, but have at least a stage effort of 4
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input_size = max(1,int(self.predriver_size/self.stage_effort))
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self.inv = pinv(size=input_size, height=self.row_height)
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self.add_mod(self.inv)
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self.inv1 = pinv(size=self.predriver_size, height=self.row_height)
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self.add_mod(self.inv1)
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self.inv2 = pinv(size=self.driver_size, height=self.row_height)
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self.add_mod(self.inv2)
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def create_insts(self):
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# Create INV1 (capacitance shield)
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self.inv1_inst=self.add_inst(name="buf_inv1",
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mod=self.inv)
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self.connect_inst(["A", "zb_int", "vdd", "gnd"])
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self.inv2_inst=self.add_inst(name="buf_inv2",
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mod=self.inv1)
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self.connect_inst(["zb_int", "z_int", "vdd", "gnd"])
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self.inv3_inst=self.add_inst(name="buf_inv3",
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mod=self.inv2)
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self.connect_inst(["z_int", "Zb", "vdd", "gnd"])
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self.inv4_inst=self.add_inst(name="buf_inv4",
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mod=self.inv2)
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self.connect_inst(["zb_int", "Z", "vdd", "gnd"])
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def place_modules(self):
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# Add INV1 to the right (capacitance shield)
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self.inv1_inst.place(vector(0,0))
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# Add INV2 to the right
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self.inv2_inst.place(vector(self.inv1_inst.rx(),0))
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# Add INV3 to the right
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self.inv3_inst.place(vector(self.inv2_inst.rx(),0))
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# Add INV4 to the bottom
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self.inv4_inst.place(offset=vector(self.inv2_inst.rx(),2*self.inv2.height),
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mirror = "MX")
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def route_wires(self):
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# inv1 Z to inv2 A
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z1_pin = self.inv1_inst.get_pin("Z")
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a2_pin = self.inv2_inst.get_pin("A")
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mid_point = vector(z1_pin.cx(), a2_pin.cy())
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self.add_path("metal1", [z1_pin.center(), mid_point, a2_pin.center()])
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# inv2 Z to inv3 A
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z2_pin = self.inv2_inst.get_pin("Z")
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a3_pin = self.inv3_inst.get_pin("A")
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mid_point = vector(z2_pin.cx(), a3_pin.cy())
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self.add_path("metal1", [z2_pin.center(), mid_point, a3_pin.center()])
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# inv1 Z to inv4 A (up and over)
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z1_pin = self.inv1_inst.get_pin("Z")
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a4_pin = self.inv4_inst.get_pin("A")
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mid_point = vector(z1_pin.cx(), a4_pin.cy())
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self.add_wire(("metal1","via1","metal2"), [z1_pin.center(), mid_point, a4_pin.center()])
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self.add_via_center(layers=("metal1","via1","metal2"),
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offset=z1_pin.center())
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def add_layout_pins(self):
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# Continous vdd rail along with label.
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vdd_pin=self.inv1_inst.get_pin("vdd")
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self.add_layout_pin(text="vdd",
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layer="metal1",
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offset=vdd_pin.ll().scale(0,1),
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width=self.width,
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height=vdd_pin.height())
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# Continous vdd rail along with label.
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gnd_pin=self.inv4_inst.get_pin("gnd")
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self.add_layout_pin(text="gnd",
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layer="metal1",
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offset=gnd_pin.ll().scale(0,1),
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width=self.width,
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height=gnd_pin.height())
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# Continous gnd rail along with label.
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gnd_pin=self.inv1_inst.get_pin("gnd")
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self.add_layout_pin(text="gnd",
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layer="metal1",
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offset=gnd_pin.ll().scale(0,1),
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width=self.width,
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height=vdd_pin.height())
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z_pin = self.inv4_inst.get_pin("Z")
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self.add_layout_pin_rect_center(text="Z",
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layer="metal2",
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offset=z_pin.center())
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self.add_via_center(layers=("metal1","via1","metal2"),
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offset=z_pin.center())
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zb_pin = self.inv3_inst.get_pin("Z")
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self.add_layout_pin_rect_center(text="Zb",
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layer="metal2",
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offset=zb_pin.center())
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self.add_via_center(layers=("metal1","via1","metal2"),
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offset=zb_pin.center())
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a_pin = self.inv1_inst.get_pin("A")
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self.add_layout_pin_rect_center(text="A",
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layer="metal2",
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offset=a_pin.center())
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self.add_via_center(layers=("metal1","via1","metal2"),
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offset=a_pin.center())
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def analytical_delay(self, slew, load=0.0):
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""" Calculate the analytical delay of DFF-> INV -> INV """
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inv1_delay = self.inv1.analytical_delay(slew=slew, load=self.inv2.input_load())
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inv2_delay = self.inv2.analytical_delay(slew=inv1_delay.slew, load=load)
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return inv1_delay + inv2_delay
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