mirror of https://github.com/VLSIDA/OpenRAM.git
158 lines
6.5 KiB
Python
158 lines
6.5 KiB
Python
from modules import sram_config
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from math import ceil
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import re
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class fake_sram(sram_config):
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"""
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This is an SRAM class that doesn't actually create an instance.
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It will read neccessary members from HTML file from a previous run.
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"""
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def __init__(self, name, word_size, num_words, write_size=None, num_banks=1,
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words_per_row=None, num_spare_rows=0, num_spare_cols=0):
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self.name = name
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self.word_size = word_size
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self.num_words = num_words
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# Don't add a write mask if it is the same size as the data word
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if write_size and write_size==word_size:
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self.write_size = None
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else:
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self.write_size = write_size
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self.num_banks = num_banks
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self.num_spare_rows = num_spare_rows
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self.num_spare_cols = num_spare_cols
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try:
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from tech import array_row_multiple
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self.array_row_multiple = array_row_multiple
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except ImportError:
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self.array_row_multiple = 1
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try:
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from tech import array_col_multiple
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self.array_col_multiple = array_col_multiple
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except ImportError:
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self.array_col_multiple = 1
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if self.write_size:
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self.num_wmasks = int(ceil(self.word_size / self.write_size))
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else:
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self.num_wmasks = 0
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if not self.num_spare_cols:
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self.num_spare_cols = 0
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if not self.num_spare_rows:
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self.num_spare_rows = 0
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# This will get over-written when we determine the organization
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self.words_per_row = words_per_row
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self.compute_sizes()
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def setup_multiport_constants(self):
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"""
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Taken from ../base/design.py
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These are contants and lists that aid multiport design.
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Ports are always in the order RW, W, R.
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Port indices start from 0 and increment.
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A first RW port will have clk0, csb0, web0, addr0, data0
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A first W port (with no RW ports) will be: clk0, csb0, addr0, data0
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"""
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total_ports = self.num_rw_ports + self.num_w_ports + self.num_r_ports
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# These are the read/write port indices.
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self.readwrite_ports = []
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# These are the read/write and write-only port indices
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self.write_ports = []
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# These are the write-only port indices.
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self.writeonly_ports = []
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# These are the read/write and read-only port indices
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self.read_ports = []
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# These are the read-only port indices.
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self.readonly_ports = []
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# These are all the ports
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self.all_ports = list(range(total_ports))
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# The order is always fixed as RW, W, R
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port_number = 0
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for port in range(self.num_rw_ports):
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self.readwrite_ports.append(port_number)
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self.write_ports.append(port_number)
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self.read_ports.append(port_number)
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port_number += 1
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for port in range(self.num_w_ports):
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self.write_ports.append(port_number)
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self.writeonly_ports.append(port_number)
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port_number += 1
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for port in range(self.num_r_ports):
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self.read_ports.append(port_number)
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self.readonly_ports.append(port_number)
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port_number += 1
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def parse_html(self, filename):
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"""
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Parse the HTML file generated from previous SRAM generation
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and populate the members
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"""
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with open(filename, 'r') as html:
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for line in html:
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if 'Ports and Configuration' in line:
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configRE = re.compile(r'<tr><td>(\w*)</td><td>(\w*)</td></tr>')
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values = configRE.finditer(line)
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for val in values:
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if val.group(1) == 'WORD_SIZE':
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self.word_size = int(val.group(2))
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elif val.group(1) == 'NUM_WORDS':
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self.num_words = int(val.group(2))
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elif val.group(1) == 'NUM_BANKS':
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self.num_banks = int(val.group(2))
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elif val.group(1) == 'NUM_RW_PORTS':
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self.num_rw_ports = int(val.group(2))
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elif val.group(1) == 'NUM_R_PORTS':
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self.num_r_ports = int(val.group(2))
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elif val.group(1) == 'NUM_W_PORTS':
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self.num_w_ports = int(val.group(2))
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elif val.group(1) == 'Area (µm<sup>2</sup>)':
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self.height = int(val.group(2) ** 0.5)
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self.width = int(val.group(2) ** 0.5)
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self.compute_sizes()
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def generate_pins(self):
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self.pins = ['vdd', 'gnd']
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self.pins.extend(['clk{}'.format(port) for port in range(
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self.num_rw_ports + self.num_r_ports + self.num_w_ports)])
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for port in range(self.num_rw_ports):
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self.pins.extend(['din{0}[{1}]]'.format(port, bit)
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for bit in range(self.num_cols)])
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self.pins.extend(['dout{0}[{1}]]'.format(port, bit)
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for bit in range(self.num_cols)])
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self.pins.extend(['addr{0}[{1}]]'.format(port, bit)
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for bit in range(self.addr_size)])
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if self.num_wmasks != 0:
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self.pins.extend(['wmask{0}[{1}]]'.format(port, bit)
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for bit in range(self.num_wmasks)])
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self.pins.extend(['csb{}'.format(port), 'web{}'.format(port)])
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start_port = self.num_rw_ports
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for port in range(start_port, start_port + self.num_r_ports):
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self.pins.extend(['dout{0}[{1}]]'.format(port, bit)
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for bit in range(self.num_cols)])
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self.pins.extend(['addr{0}[{1}]]'.format(port, bit)
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for bit in range(self.addr_size)])
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self.pins.extend(['csb{}'.format(port)])
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start_port += self.num_r_ports
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for port in range(start_port, start_port + self.num_w_ports):
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self.pins.extend(['din{0}[{1}]]'.format(port, bit)
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for bit in range(self.num_cols)])
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self.pins.extend(['addr{0}[{1}]]'.format(port, bit)
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for bit in range(self.addr_size)])
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if self.num_wmasks != 0:
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self.pins.extend(['wmask{0}[{1}]]'.format(port, bit)
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for bit in range(self.num_wmasks)])
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self.pins.extend(['csb{}'.format(port), 'web{}'.format(port)])
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