mirror of https://github.com/VLSIDA/OpenRAM.git
91 lines
3.2 KiB
Python
91 lines
3.2 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2023 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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from .rom_base_cell import rom_base_cell
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from .pgate import pgate
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from openram.base import vector
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from openram import OPTS
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from openram.sram_factory import factory
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from openram.tech import drc
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class rom_precharge_cell(rom_base_cell):
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def __init__(self, name="", bitline_layer="m1", supply_layer="li"):
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self.supply_layer = supply_layer
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super().__init__(name=name, bitline_layer=bitline_layer)
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def create_layout(self):
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super().create_layout()
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self.place_tap()
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self.extend_well()
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def add_modules(self):
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if OPTS.tech_name == "sky130":
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width = pgate.nearest_bin("pmos", drc["minwidth_tx"])
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else:
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width = drc("minwidth_tx")
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self.pmos = factory.create(module_type="ptx",
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module_name="pre_pmos_mod",
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tx_type="pmos",
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width=width,
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add_source_contact=self.supply_layer,
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add_drain_contact=self.bitline_layer
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)
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def create_tx(self):
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self.cell_inst = self.add_inst( name="precharge_pmos",
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mod=self.pmos,
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)
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self.connect_inst(["bitline", "gate", "vdd", "vdd"])
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def add_pins(self):
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pin_list = ["vdd", "gate", "bitline"]
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dir_list = ["POWER", "INPUT", "OUTPUT"]
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self.add_pin_list(pin_list, dir_list)
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def setup_drc_offsets(self):
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self.poly_size = (self.cell_inst.width + self.active_space) - (self.cell_inst.height + 2 * self.poly_extend_active)
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def extend_well(self):
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well_y = self.get_pin("vdd").cy() - 0.5 * self.tap.height - self.nwell_enclose_active
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well_ll = vector(0, well_y)
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height = self.get_pin("D").cy() + self.nwell_enclose_active - well_y
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self.add_rect("nwell", well_ll, self.width , height)
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def place_tap(self):
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source = self.cell_inst.get_pin("S")
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tap_y = source.cy() - self.contact_width - 5 * self.active_enclose_contact - self.active_space
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self.tap_offset = abs(tap_y)
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pos = vector(source.cx(), tap_y )
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self.tap = self.add_via_center(layers=self.active_stack,
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offset=pos,
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implant_type="n",
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well_type="n",
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directions="nonpref")
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self.add_via_stack_center(offset=pos,
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from_layer=self.active_stack[2],
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to_layer=self.supply_layer)
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bitline_offset = vector( 1.5 * (drc("minwidth_{}".format(self.bitline_layer)) + drc("{0}_to_{0}".format(self.bitline_layer))) ,0)
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self.add_layout_pin_rect_center("vdd", self.supply_layer, pos - bitline_offset)
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self.add_path(self.supply_layer, [self.get_pin("vdd").center(), pos, self.get_pin("S").center()])
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self.remove_layout_pin("S")
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def place_bitline(self):
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pass
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def short_gate(self):
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pass |