mirror of https://github.com/VLSIDA/OpenRAM.git
221 lines
8.0 KiB
Python
221 lines
8.0 KiB
Python
import contact
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import pgate
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import debug
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from tech import drc, parameter, spice
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from vector import vector
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from math import ceil
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from globals import OPTS
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from utils import round_to_grid
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import logical_effort
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from sram_factory import factory
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class ptristate_inv(pgate.pgate):
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"""
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ptristate generates gds of a parametrically sized tristate inverter.
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There is some flexibility in the size, but we do not allow multiple fingers
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to fit in the cell height.
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"""
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def __init__(self, name, size=1, height=None):
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debug.info(2, "creating ptristate inv {0} with size of {1}".format(name, size))
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self.add_comment("size: {}".format(size))
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# We are 2x since there are two series devices
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self.size = 2*size
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self.nmos_size = size
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self.beta = parameter["beta"]
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self.pmos_size = self.beta*size
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self.nmos_width = self.nmos_size * drc("minwidth_tx")
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self.pmos_width = self.pmos_size * drc("minwidth_tx")
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# Creates the netlist and layout
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pgate.pgate.__init__(self, name, height)
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def create_netlist(self):
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""" Calls all functions related to the generation of the netlist """
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self.add_pins()
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self.add_ptx()
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self.create_ptx()
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def create_layout(self):
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""" Calls all functions related to the generation of the layout """
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self.setup_layout_constants()
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self.route_supply_rails()
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self.place_ptx()
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self.add_well_contacts()
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self.extend_wells(self.well_pos)
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self.connect_rails()
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self.route_inputs()
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self.route_outputs()
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def add_pins(self):
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""" Adds pins for spice netlist """
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self.add_pin_list(["in", "out", "en", "en_bar", "vdd", "gnd"])
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def setup_layout_constants(self):
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"""
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Pre-compute some handy layout parameters.
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"""
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# Compute the other pmos2 location, but determining offset to overlap the
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# source and drain pins
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self.overlap_offset = self.pmos.get_pin("D").ll() - self.pmos.get_pin("S").ll()
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# Two PMOS devices and a well contact. Separation between each.
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# Enclosure space on the sides.
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self.well_width = 2*self.pmos.active_width + drc("well_enclosure_active")
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# Add an extra space because we route the output on the right of the S/D
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self.width = self.well_width + 0.5*self.m1_space
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# Height is an input parameter, so it is not recomputed.
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# Make sure we can put a well above and below
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self.top_bottom_space = max(contact.well.width, contact.well.height)
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def add_ptx(self):
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""" Create the PMOS and NMOS transistors. """
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self.nmos = factory.create(module_type="ptx",
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width=self.nmos_width,
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mults=1,
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tx_type="nmos")
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self.add_mod(self.nmos)
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self.pmos = factory.create(module_type="ptx",
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width=self.pmos_width,
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mults=1,
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tx_type="pmos")
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self.add_mod(self.pmos)
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def route_supply_rails(self):
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""" Add vdd/gnd rails to the top and bottom. """
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self.add_layout_pin_rect_center(text="gnd",
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layer="metal1",
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offset=vector(0.5*self.width,0),
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width=self.width)
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self.add_layout_pin_rect_center(text="vdd",
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layer="metal1",
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offset=vector(0.5*self.width,self.height),
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width=self.width)
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def create_ptx(self):
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"""
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Create the PMOS and NMOS netlist.
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"""
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# These are the inverter PMOS/NMOS
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self.pmos1_inst=self.add_inst(name="ptri_pmos1", mod=self.pmos)
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self.connect_inst(["vdd", "in", "n1", "vdd"])
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self.nmos1_inst=self.add_inst(name="ptri_nmos1", mod=self.nmos)
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self.connect_inst(["gnd", "in", "n2", "gnd"])
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# These are the tristate PMOS/NMOS
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self.pmos2_inst = self.add_inst(name="ptri_pmos2", mod=self.pmos)
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self.connect_inst(["out", "en_bar", "n1", "vdd"])
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self.nmos2_inst=self.add_inst(name="ptri_nmos2", mod=self.nmos)
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self.connect_inst(["out", "en", "n2", "gnd"])
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def place_ptx(self):
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"""
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Place PMOS and NMOS to the layout at the upper-most and lowest position
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to provide maximum routing in channel
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"""
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pmos_yoff = self.height - self.pmos.active_height - self.top_bottom_space - 0.5*contact.well.height
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nmos_yoff = self.top_bottom_space + 0.5*contact.well.height
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# Tristate transistors
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pmos1_pos = vector(self.pmos.active_offset.x, pmos_yoff)
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self.pmos1_inst.place(pmos1_pos)
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nmos1_pos = vector(self.pmos.active_offset.x, nmos_yoff)
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self.nmos1_inst.place(nmos1_pos)
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# Inverter transistors
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self.pmos2_pos = pmos1_pos + self.overlap_offset
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self.pmos2_inst.place(self.pmos2_pos)
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self.nmos2_pos = nmos1_pos + self.overlap_offset
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self.nmos2_inst.place(self.nmos2_pos)
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# Output position will be in between the PMOS and NMOS
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self.output_pos = vector(0, 0.5*(pmos_yoff + nmos_yoff + self.nmos.height))
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# This will help with the wells
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self.well_pos = vector(0,self.nmos1_inst.uy())
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def route_inputs(self):
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""" Route the gates """
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self.route_input_gate(self.pmos1_inst, self.nmos1_inst, self.output_pos.y, "in", position="farleft")
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self.route_single_gate(self.pmos2_inst, "en_bar", position="left")
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self.route_single_gate(self.nmos2_inst, "en", position="left")
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def route_outputs(self):
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""" Route the output (drains) together. """
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nmos_drain_pin = self.nmos2_inst.get_pin("D")
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pmos_drain_pin = self.pmos2_inst.get_pin("D")
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nmos_drain_pos = nmos_drain_pin.lr()
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pmos_drain_pos = pmos_drain_pin.ur()
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self.add_layout_pin(text="out",
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layer="metal1",
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offset=nmos_drain_pos,
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height=pmos_drain_pos.y-nmos_drain_pos.y)
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def add_well_contacts(self):
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""" Add n/p well taps to the layout and connect to supplies AFTER the wells are created """
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layer_stack = ("active", "contact", "metal1")
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drain_pos = self.nmos1_inst.get_pin("S").center()
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vdd_pos = self.get_pin("vdd").center()
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self.nwell_contact=self.add_via_center(layers=layer_stack,
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offset=vector(drain_pos.x,vdd_pos.y),
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implant_type="n",
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well_type="n")
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gnd_pos = self.get_pin("gnd").center()
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self.pwell_contact=self.add_via_center(layers=layer_stack,
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offset=vector(drain_pos.x,gnd_pos.y),
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implant_type="p",
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well_type="p")
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def connect_rails(self):
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""" Connect the nmos and pmos to its respective power rails """
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self.connect_pin_to_rail(self.nmos1_inst,"S","gnd")
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self.connect_pin_to_rail(self.pmos1_inst,"S","vdd")
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def analytical_delay(self, corner, slew, load=0.0):
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from tech import spice
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r = spice["min_tx_r"]
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c_para = spice["min_tx_drain_c"]
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return self.cal_delay_with_rc(corner, r = r, c = c_para+load, slew = slew)
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def analytical_power(self, corner, load):
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"""Returns dynamic and leakage power. Results in nW"""
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#Power in this module currently not defined. Returns 0 nW (leakage and dynamic).
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total_power = self.return_power()
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return total_power
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def input_load(self):
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return 9*spice["min_tx_gate_c"]
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