mirror of https://github.com/VLSIDA/OpenRAM.git
215 lines
7.8 KiB
Python
215 lines
7.8 KiB
Python
import debug
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import pgate
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import math
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from tech import drc
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from math import log
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from vector import vector
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from globals import OPTS
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from sram_factory import factory
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class pdriver(pgate.pgate):
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"""
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This instantiates an even or odd number of inverters sized for driving a load.
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"""
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def __init__(self, name, neg_polarity=False, fanout=0, size_list=None, height=None):
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debug.info(1, "creating pdriver {}".format(name))
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self.stage_effort = 3
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self.height = height
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self.neg_polarity = neg_polarity
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self.size_list = size_list
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self.fanout = fanout
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if size_list == None and self.fanout == 0:
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debug.error("Either fanout or size list must be specified.", -1)
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if self.size_list and self.fanout != 0:
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debug.error("Cannot specify both size_list and fanout.", -1)
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if self.size_list and self.neg_polarity:
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debug.error("Cannot specify both size_list and neg_polarity.", -1)
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# Creates the netlist and layout
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pgate.pgate.__init__(self, name, height)
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def compute_sizes(self):
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# size_list specified
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if self.size_list:
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self.num_stages = len(self.size_list)
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else:
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# Find the optimal number of stages for the given effort
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self.num_stages = max(1,int(round(log(self.fanout)/log(self.stage_effort))))
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# Increase the number of stages if we need to fix polarity
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if self.neg_polarity and (self.num_stages%2==0):
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self.num_stages += 1
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elif not self.neg_polarity and (self.num_stages%2):
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self.num_stages += 1
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self.size_list = []
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# compute sizes backwards from the fanout
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fanout_prev = self.fanout
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for x in range(self.num_stages):
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fanout_prev = max(round(fanout_prev/self.stage_effort),1)
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self.size_list.append(fanout_prev)
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# reverse the sizes to be from input to output
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self.size_list.reverse()
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def create_netlist(self):
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self.compute_sizes()
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self.add_comment("sizes: {}".format(str(self.size_list)))
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self.add_pins()
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self.add_modules()
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self.create_insts()
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def create_layout(self):
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self.place_modules()
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self.route_wires()
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self.add_layout_pins()
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self.width = self.inv_inst_list[-1].rx()
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self.height = self.inv_inst_list[0].height
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def add_pins(self):
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self.add_pin("A")
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self.add_pin("Z")
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self.add_pin("vdd")
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self.add_pin("gnd")
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def add_modules(self):
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self.inv_list = []
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for size in self.size_list:
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temp_inv = factory.create(module_type="pinv", size=size, height=self.height)
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self.inv_list.append(temp_inv)
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self.add_mod(temp_inv)
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def create_insts(self):
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self.inv_inst_list = []
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for x in range(1,self.num_stages+1):
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# Create first inverter
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if x == 1:
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zbx_int = "Zb{}_int".format(x);
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self.inv_inst_list.append(self.add_inst(name="buf_inv{}".format(x),
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mod=self.inv_list[x-1]))
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if self.num_stages == 1:
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self.connect_inst(["A", "Z", "vdd", "gnd"])
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else:
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self.connect_inst(["A", zbx_int, "vdd", "gnd"])
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# Create last inverter
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elif x == self.num_stages:
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zbn_int = "Zb{}_int".format(x-1);
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self.inv_inst_list.append(self.add_inst(name="buf_inv{}".format(x),
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mod=self.inv_list[x-1]))
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self.connect_inst([zbn_int, "Z", "vdd", "gnd"])
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# Create middle inverters
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else:
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zbx_int = "Zb{}_int".format(x-1);
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zbn_int = "Zb{}_int".format(x);
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self.inv_inst_list.append(self.add_inst(name="buf_inv{}".format(x),
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mod=self.inv_list[x-1]))
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self.connect_inst([zbx_int, zbn_int, "vdd", "gnd"])
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def place_modules(self):
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# Add the first inverter at the origin
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self.inv_inst_list[0].place(vector(0,0))
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# Add inverters to the right of the previous inverter
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for x in range(1,len(self.inv_inst_list)):
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self.inv_inst_list[x].place(vector(self.inv_inst_list[x-1].rx(),0))
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def route_wires(self):
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z_inst_list = []
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a_inst_list = []
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# inv_current Z to inv_next A
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for x in range(0,len(self.inv_inst_list)-1):
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z_inst_list.append(self.inv_inst_list[x].get_pin("Z"))
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a_inst_list.append(self.inv_inst_list[x+1].get_pin("A"))
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mid_point = vector(z_inst_list[x].cx(), a_inst_list[x].cy())
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self.add_path("metal1", [z_inst_list[x].center(), mid_point, a_inst_list[x].center()])
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def add_layout_pins(self):
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# Continous vdd rail along with label.
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vdd_pin=self.inv_inst_list[0].get_pin("vdd")
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self.add_layout_pin(text="vdd",
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layer="metal1",
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offset=vdd_pin.ll().scale(0,1),
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width=self.width,
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height=vdd_pin.height())
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# Continous gnd rail along with label.
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gnd_pin=self.inv_inst_list[0].get_pin("gnd")
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self.add_layout_pin(text="gnd",
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layer="metal1",
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offset=gnd_pin.ll().scale(0,1),
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width=self.width,
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height=vdd_pin.height())
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z_pin = self.inv_inst_list[len(self.inv_inst_list)-1].get_pin("Z")
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self.add_layout_pin_rect_center(text="Z",
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layer=z_pin.layer,
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offset=z_pin.center(),
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width = z_pin.width(),
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height = z_pin.height())
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a_pin = self.inv_inst_list[0].get_pin("A")
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self.add_layout_pin_rect_center(text="A",
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layer=a_pin.layer,
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offset=a_pin.center(),
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width = a_pin.width(),
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height = a_pin.height())
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def input_load(self):
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return self.inv_list[0].input_load()
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def analytical_delay(self, corner, slew, load=0.0):
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"""Calculate the analytical delay of INV1 -> ... -> INVn"""
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cout_list = []
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for prev_inv,inv in zip(self.inv_list, self.inv_list[1:]):
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cout_list.append(inv.input_load())
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cout_list.append(load)
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input_slew = slew
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delays = []
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for inv,cout in zip(self.inv_list,cout_list):
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delays.append(inv.analytical_delay(corner, slew=input_slew, load=cout))
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input_slew = delays[-1].slew
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delay = delays[0]
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for i in range(len(delays)-1):
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delay += delays[i]
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return delay
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def get_stage_efforts(self, external_cout, inp_is_rise=False):
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"""Get the stage efforts of the A -> Z path"""
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cout_list = []
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for prev_inv,inv in zip(self.inv_list, self.inv_list[1:]):
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cout_list.append(inv.get_cin())
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cout_list.append(external_cout)
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stage_effort_list = []
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last_inp_is_rise = inp_is_rise
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for inv,cout in zip(self.inv_list,cout_list):
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stage = inv.get_stage_effort(cout, last_inp_is_rise)
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stage_effort_list.append(stage)
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last_inp_is_rise = stage.is_rise
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return stage_effort_list
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def get_cin(self):
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"""Returns the relative capacitance of the input"""
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return self.inv_list[0].get_cin()
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