mirror of https://github.com/VLSIDA/OpenRAM.git
130 lines
4.1 KiB
Python
130 lines
4.1 KiB
Python
import optparse
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import getpass
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import os
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class options(optparse.Values):
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"""
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Class for holding all of the OpenRAM options. All of these options can be over-riden in a configuration file
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that is the sole required command-line positional argument for openram.py.
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"""
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###################
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# Configuration options
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###################
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# This is the technology directory.
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openram_tech = ""
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# This is the name of the technology.
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tech_name = ""
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# Port configuration (1-2 ports allowed)
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num_rw_ports = 1
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num_r_ports = 0
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num_w_ports = 0
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# These will get initialized by the user or the tech file
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supply_voltages = ""
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temperatures = ""
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process_corners = ""
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# Size parameters must be specified by user in config file.
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#num_words = 0
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#word_size = 0
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# You can manually specify banks, but it is better to auto-detect it.
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num_banks = 1
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###################
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# Optimization options
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###################
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# Uses the delay chain size in the tech.py file rather automatic sizing.
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use_tech_delay_chain_size = False
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###################
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# Debug options.
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###################
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# This is the temp directory where all intermediate results are stored.
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try:
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# If user defined the temporary location in their environment, use it
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openram_temp = os.path.abspath(os.environ.get("OPENRAM_TMP"))
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except:
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# Else use a unique temporary directory
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openram_temp = "/tmp/openram_{0}_{1}_temp/".format(getpass.getuser(),os.getpid())
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# This is the verbosity level to control debug information. 0 is none, 1
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# is minimal, etc.
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debug_level = 0
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###################
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# Run-time vs accuracy options.
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# Default, sacrifice accuracy/completeness for speed.
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# Must turn on options for verification, final routing, etc.
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###################
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# When enabled, layout is not generated (and no DRC or LVS are performed)
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netlist_only = False
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# Whether we should do the final power routing
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route_supplies = False
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# This determines whether LVS and DRC is checked at all.
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check_lvsdrc = False
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# This determines whether LVS and DRC is checked for every submodule.
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inline_lvsdrc = False
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# Remove noncritical memory cells for characterization speed-up
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trim_netlist = True
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# Run with extracted parasitics
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use_pex = False
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###################
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# Tool options
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###################
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# Variable to select the variant of spice
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spice_name = ""
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# The spice executable being used which is derived from the user PATH.
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spice_exe = ""
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# Variable to select the variant of drc, lvs, pex
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drc_name = ""
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lvs_name = ""
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pex_name = ""
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# The DRC/LVS/PEX executable being used which is derived from the user PATH.
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drc_exe = None
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lvs_exe = None
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pex_exe = None
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# Should we print out the banner at startup
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print_banner = True
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# Use detailed LEF blockages
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detailed_blockages = True
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# Define the output file paths
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output_path = "."
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# Define the output file base name
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output_name = ""
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# Use analytical delay models by default rather than (slow) characterization
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analytical_delay = True
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# Purge the temp directory after a successful run (doesn't purge on errors, anyhow)
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purge_temp = True
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###################
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# These are the default modules that can be over-riden
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###################
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bank_select = "bank_select"
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bitcell_array = "bitcell_array"
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bitcell = "bitcell"
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column_mux_array = "single_level_column_mux_array"
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control_logic = "control_logic"
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decoder = "hierarchical_decoder"
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delay_chain = "delay_chain"
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dff_array = "dff_array"
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dff = "dff"
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precharge_array = "precharge_array"
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ptx = "ptx"
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replica_bitcell = "replica_bitcell"
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replica_bitline = "replica_bitline"
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sense_amp_array = "sense_amp_array"
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sense_amp = "sense_amp"
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tri_gate_array = "tri_gate_array"
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tri_gate = "tri_gate"
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wordline_driver = "wordline_driver"
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write_driver_array = "write_driver_array"
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write_driver = "write_driver"
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