mirror of https://github.com/VLSIDA/OpenRAM.git
40 lines
1.2 KiB
Python
40 lines
1.2 KiB
Python
import debug
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import design
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import utils
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from tech import GDS,layer
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class tri_gate(design.design):
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"""
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This module implements the tri gate cell used in the design for
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bit-line isolation. It is a hand-made cell, so the layout and
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netlist should be available in the technology library.
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"""
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pin_names = ["in", "en", "en_bar", "out", "gnd", "vdd"]
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(width,height) = utils.get_libcell_size("tri_gate", GDS["unit"], layer["boundary"])
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pin_map = utils.get_libcell_pins(pin_names, "tri_gate", GDS["unit"], layer["boundary"])
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unique_id = 1
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def __init__(self, name=""):
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if name=="":
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name = "tri{0}".format(tri_gate.unique_id)
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tri_gate.unique_id += 1
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design.design.__init__(self, name)
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debug.info(2, "Create tri_gate")
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self.width = tri_gate.width
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self.height = tri_gate.height
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self.pin_map = tri_gate.pin_map
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def analytical_delay(self, slew, load=0.0):
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from tech import spice
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r = spice["min_tx_r"]
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c_para = spice["min_tx_drain_c"]
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return self.cal_delay_with_rc(r = r, c = c_para+load, slew = slew)
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def input_load(self):
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return 9*spice["min_tx_gate_c"]
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