mirror of https://github.com/VLSIDA/OpenRAM.git
41 lines
1.3 KiB
Python
41 lines
1.3 KiB
Python
import optparse
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import getpass
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import os
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class options(optparse.Values):
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"""
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Class for holding all of the OpenRAM options.
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"""
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# This is the technology directory.
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openram_tech = ""
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# This is the name of the technology.
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tech_name = ""
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# This is the temp directory where all intermediate results are stored.
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openram_temp = "/tmp/openram_{0}_{1}_temp/".format(getpass.getuser(),os.getpid())
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# This is the verbosity level to control debug information. 0 is none, 1
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# is minimal, etc.
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debug_level = 0
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# This determines whether LVS and DRC is checked for each submodule.
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check_lvsdrc = True
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# Variable to select the variant of spice
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spice_name = ""
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# Should we print out the banner at startup
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print_banner = True
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# The DRC/LVS/PEX executable being used which is derived from the user PATH.
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drc_exe = ""
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lvs_exe = ""
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pex_exe = ""
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# The spice executable being used which is derived from the user PATH.
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spice_exe = ""
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# Run with extracted parasitics
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use_pex = False
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# Remove noncritical memory cells for characterization speed-up
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trim_netlist = True
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# Define the output file paths
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output_path = ""
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# Define the output file base name
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output_name = ""
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# Use analytical delay models by default rather than (slow) characterization
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analytical_delay = True
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