mirror of https://github.com/VLSIDA/OpenRAM.git
415 lines
18 KiB
Python
415 lines
18 KiB
Python
import os
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import sys
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import re
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import debug
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import tech
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import math
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import setup_hold
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import delay
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import charutils as ch
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import tech
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import numpy as np
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from trim_spice import trim_spice
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from globals import OPTS
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class lib:
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""" lib file generation."""
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def __init__(self, libname, sram, spfile, use_model=OPTS.analytical_delay):
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self.sram = sram
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self.sp_file = spfile
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self.use_model = use_model
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self.name = sram.name
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self.num_words = sram.num_words
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self.word_size = sram.word_size
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self.addr_size = sram.addr_size
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# Set up to trim the netlist here if that is enabled
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if OPTS.trim_netlist:
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self.sim_sp_file = "{}reduced.sp".format(OPTS.openram_temp)
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self.trimsp=trim_spice(self.sp_file, self.sim_sp_file)
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self.trimsp.set_configuration(self.sram.num_banks,
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self.sram.num_rows,
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self.sram.num_cols,
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self.sram.word_size)
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else:
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# Else, use the non-reduced netlist file for simulation
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self.sim_sp_file = self.sp_file
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# These are the parameters to determine the table sizes
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#self.load_scales = np.array([0.1, 0.25, 0.5, 1, 2, 4, 8])
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self.load_scales = np.array([0.25, 1, 8])
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#self.load_scales = np.array([0.25, 1])
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self.load = tech.spice["FF_in_cap"]
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self.loads = self.load_scales*self.load
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debug.info(1,"Loads: {0}".format(self.loads))
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#self.slew_scales = np.array([0.1, 0.25, 0.5, 1, 2, 4, 8])
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self.slew_scales = np.array([0.25, 1, 8])
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#self.slew_scales = np.array([0.25, 1])
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self.slew = tech.spice["rise_time"]
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self.slews = self.slew_scales*self.slew
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debug.info(1,"Slews: {0}".format(self.slews))
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debug.info(1,"Writing to {0}".format(libname))
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self.lib = open(libname, "w")
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self.write_header()
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self.write_data_bus()
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self.write_addr_bus()
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self.write_control_pins()
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self.write_clk()
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self.lib.close()
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def write_header(self):
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""" Write the header information """
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self.lib.write("library ({0}_lib)".format(self.name))
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self.lib.write("{\n")
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self.lib.write(" delay_model : \"table_lookup\";\n")
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self.write_units()
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self.write_defaults()
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self.write_LUT_templates()
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self.lib.write(" default_operating_conditions : TT; \n")
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self.write_bus()
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self.lib.write("cell ({0})".format(self.name))
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self.lib.write("{\n")
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self.lib.write(" memory(){ \n")
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self.lib.write(" type : ram;\n")
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self.lib.write(" address_width : {0};\n".format(self.addr_size))
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self.lib.write(" word_width : {0};\n".format(self.word_size))
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self.lib.write(" }\n")
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self.lib.write(" interface_timing : true;\n")
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self.lib.write(" dont_use : true;\n")
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self.lib.write(" map_only : true;\n")
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self.lib.write(" dont_touch : true;\n")
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self.lib.write(" area : {0};\n\n".format(self.sram.width * self.sram.height))
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def write_units(self):
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""" Adds default units for time, voltage, current,..."""
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self.lib.write(" time_unit : \"1ns\" ;\n")
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self.lib.write(" voltage_unit : \"1v\" ;\n")
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self.lib.write(" current_unit : \"1mA\" ;\n")
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self.lib.write(" resistance_unit : \"1kohm\" ;\n")
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self.lib.write(" capacitive_load_unit(1 ,fF) ;\n")
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self.lib.write(" leakage_power_unit : \"1mW\" ;\n")
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self.lib.write(" pulling_resistance_unit :\"1kohm\" ;\n")
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self.lib.write(" operating_conditions(TT){\n")
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self.lib.write(" voltage : {0} ;\n".format(tech.spice["supply_voltage"]))
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self.lib.write(" temperature : 25.000 ;\n")
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self.lib.write(" }\n\n")
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def write_defaults(self):
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""" Adds default values for slew and capacitance."""
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self.lib.write(" input_threshold_pct_fall : 50.0 ;\n")
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self.lib.write(" output_threshold_pct_fall : 50.0 ;\n")
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self.lib.write(" input_threshold_pct_rise : 50.0 ;\n")
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self.lib.write(" output_threshold_pct_rise : 50.0 ;\n")
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self.lib.write(" slew_lower_threshold_pct_fall : 10.0 ;\n")
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self.lib.write(" slew_upper_threshold_pct_fall : 90.0 ;\n")
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self.lib.write(" slew_lower_threshold_pct_rise : 10.0 ;\n")
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self.lib.write(" slew_upper_threshold_pct_rise : 90.0 ;\n\n")
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self.lib.write(" default_cell_leakage_power : 0.0 ;\n")
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self.lib.write(" default_leakage_power_density : 0.0 ;\n")
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self.lib.write(" default_input_pin_cap : 1.0 ;\n")
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self.lib.write(" default_inout_pin_cap : 1.0 ;\n")
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self.lib.write(" default_output_pin_cap : 0.0 ;\n")
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self.lib.write(" default_max_transition : 0.5 ;\n")
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self.lib.write(" default_fanout_load : 1.0 ;\n")
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self.lib.write(" default_max_fanout : 4.0 ;\n")
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self.lib.write(" default_connection_class : universal ;\n\n")
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def create_list(self,values):
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""" Helper function to create quoted, line wrapped list """
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list_values = ", ".join(str(v) for v in values)
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return "\"{0}\"".format(list_values)
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def create_array(self,values, length):
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""" Helper function to create quoted, line wrapped array with each row of given length """
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# check that the length is a multiple or give an error!
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debug.check(len(values)%length == 0,"Values are not a multiple of the length. Cannot make a full array.")
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rounded_values = map(ch.round_time,values)
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split_values = [rounded_values[i:i+length] for i in range(0, len(rounded_values), length)]
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formatted_rows = map(self.create_list,split_values)
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formatted_array = ",\\\n".join(formatted_rows)
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return formatted_array
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def write_index(self, number, values):
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""" Write the index """
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quoted_string = self.create_list(values)
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self.lib.write(" index_{0}({1});\n".format(number,quoted_string))
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def write_values(self, values, row_length, indent):
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""" Write the index """
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quoted_string = self.create_array(values, row_length)
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# indent each newline plus extra spaces for word values
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indented_string = quoted_string.replace('\n', '\n' + indent +" ")
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self.lib.write("{0}values({1});\n".format(indent,indented_string))
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def write_LUT_templates(self):
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""" Adds lookup_table format (A 1x1 lookup_table)."""
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Tran = ["CELL_TABLE"]
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for i in Tran:
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self.lib.write(" lu_table_template({0})".format(i))
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self.lib.write("{\n")
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self.lib.write(" variable_1 : input_net_transition;\n")
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self.lib.write(" variable_2 : total_output_net_capacitance;\n")
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self.write_index(1,self.slews)
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self.write_index(2,self.loads)
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self.lib.write(" }\n\n")
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CONS = ["CONSTRAINT_TABLE"]
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for i in CONS:
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self.lib.write(" lu_table_template({0})".format(i))
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self.lib.write("{\n")
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self.lib.write(" variable_1 : related_pin_transition;\n")
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self.lib.write(" variable_2 : constrained_pin_transition;\n")
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self.write_index(1,self.slews)
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self.write_index(2,self.slews)
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self.lib.write(" }\n\n")
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# self.lib.write(" lu_table_template(CLK_TRAN) {\n")
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# self.lib.write(" variable_1 : constrained_pin_transition;\n")
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# self.write_index(1,self.slews)
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# self.lib.write(" }\n\n")
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# self.lib.write(" lu_table_template(TRAN) {\n")
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# self.lib.write(" variable_1 : total_output_net_capacitance;\n")
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# self.write_index(1,self.slews)
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# self.lib.write(" }\n\n")
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# CONS2 = ["INPUT_BY_TRANS_FOR_CLOCK" , "INPUT_BY_TRANS_FOR_SIGNAL"]
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# for i in CONS2:
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# self.lib.write(" power_lut_template({0})".format(i))
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# self.lib.write("{\n")
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# self.lib.write(" variable_1 : input_transition_time;\n")
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# #self.write_index(1,self.slews)
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# self.write_index(1,[self.slews[0]])
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# self.lib.write(" }\n\n")
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def write_bus(self):
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""" Adds format of DATA and ADDR bus."""
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self.lib.write("\n\n")
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self.lib.write(" type (DATA){\n")
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self.lib.write(" base_type : array;\n")
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self.lib.write(" data_type : bit;\n")
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self.lib.write(" bit_width : {0};\n".format(self.word_size))
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self.lib.write(" bit_from : 0;\n")
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self.lib.write(" bit_to : {0};\n".format(self.word_size - 1))
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self.lib.write(" }\n\n")
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self.lib.write(" type (ADDR){\n")
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self.lib.write(" base_type : array;\n")
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self.lib.write(" data_type : bit;\n")
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self.lib.write(" bit_width : {0};\n".format(self.addr_size))
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self.lib.write(" bit_from : 0;\n")
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self.lib.write(" bit_to : {0};\n".format(self.addr_size - 1))
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self.lib.write(" }\n\n")
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def write_FF_setuphold(self):
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""" Adds Setup and Hold timing results"""
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self.compute_setup_hold()
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self.lib.write(" timing(){ \n")
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self.lib.write(" timing_type : setup_rising; \n")
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self.lib.write(" related_pin : \"clk\"; \n")
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self.lib.write(" rise_constraint(CONSTRAINT_TABLE) {\n")
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rounded_values = map(ch.round_time,self.times["setup_times_LH"])
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self.write_values(rounded_values,len(self.slews)," ")
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self.lib.write(" }\n")
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self.lib.write(" fall_constraint(CONSTRAINT_TABLE) {\n")
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rounded_values = map(ch.round_time,self.times["setup_times_HL"])
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self.write_values(rounded_values,len(self.slews)," ")
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self.lib.write(" }\n")
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self.lib.write(" }\n")
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self.lib.write(" timing(){ \n")
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self.lib.write(" timing_type : hold_rising; \n")
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self.lib.write(" related_pin : \"clk\"; \n")
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self.lib.write(" rise_constraint(CONSTRAINT_TABLE) {\n")
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rounded_values = map(ch.round_time,self.times["hold_times_LH"])
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self.write_values(rounded_values,len(self.slews)," ")
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self.lib.write(" }\n")
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self.lib.write(" fall_constraint(CONSTRAINT_TABLE) {\n")
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rounded_values = map(ch.round_time,self.times["hold_times_HL"])
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self.write_values(rounded_values,len(self.slews)," ")
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self.lib.write(" }\n")
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self.lib.write(" }\n")
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def write_data_bus(self):
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""" Adds data bus timing results."""
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self.compute_delay()
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self.lib.write(" bus(DATA){\n")
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self.lib.write(" bus_type : DATA; \n")
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self.lib.write(" direction : inout; \n")
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self.lib.write(" max_capacitance : {0}; \n".format(8*tech.spice["FF_in_cap"]))
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self.lib.write(" three_state : \"!OEb & !clk\"; \n")
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self.lib.write(" memory_write(){ \n")
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self.lib.write(" address : ADDR; \n")
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self.lib.write(" clocked_on : clk; \n")
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self.lib.write(" }\n")
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self.lib.write(" memory_read(){ \n")
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self.lib.write(" address : ADDR; \n")
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self.lib.write(" }\n")
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self.lib.write(" pin(DATA[{0}:0])".format(self.word_size - 1))
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self.lib.write("{\n")
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self.lib.write(" internal_power(){\n")
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self.lib.write(" when : \"OEb & !clk\"; \n")
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self.lib.write(" rise_power(scalar){\n")
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self.lib.write(" values(\"{0}\");\n".format(self.delay["write1_power"]))
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self.lib.write(" }\n")
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self.lib.write(" fall_power(scalar){\n")
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self.lib.write(" values(\"{0}\");\n".format(self.delay["write0_power"]))
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self.lib.write(" }\n")
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self.lib.write(" }\n")
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self.write_FF_setuphold()
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self.lib.write(" internal_power(){\n")
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self.lib.write(" when : \"!OEb & !clk\"; \n")
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self.lib.write(" rise_power(scalar){\n")
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self.lib.write(" values(\"{0}\");\n".format(self.delay["read1_power"]))
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self.lib.write(" }\n")
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self.lib.write(" fall_power(scalar){\n")
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self.lib.write(" values(\"{0}\");\n".format(self.delay["read0_power"]))
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self.lib.write(" }\n")
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self.lib.write(" }\n")
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self.lib.write(" timing(){ \n")
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self.lib.write(" timing_sense : non_unate; \n")
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self.lib.write(" related_pin : \"clk\"; \n")
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self.lib.write(" timing_type : falling_edge; \n")
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self.lib.write(" cell_rise(CELL_TABLE) {\n")
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rounded_values = map(ch.round_time,self.delay["delay1"])
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self.write_values(rounded_values,len(self.loads)," ")
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self.lib.write(" }\n")
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self.lib.write(" cell_fall(CELL_TABLE) {\n")
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rounded_values = map(ch.round_time,self.delay["delay0"])
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self.write_values(rounded_values,len(self.loads)," ")
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self.lib.write(" }\n")
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self.lib.write(" rise_transition(CELL_TABLE) {\n")
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rounded_values = map(ch.round_time,self.delay["slew1"])
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self.write_values(rounded_values,len(self.loads)," ")
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self.lib.write(" }\n")
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self.lib.write(" fall_transition(CELL_TABLE) {\n")
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rounded_values = map(ch.round_time,self.delay["slew0"])
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self.write_values(rounded_values,len(self.loads)," ")
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self.lib.write(" }\n")
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self.lib.write(" }\n")
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self.lib.write(" }\n")
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self.lib.write(" }\n\n")
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def write_addr_bus(self):
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""" Adds addr bus timing results."""
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self.lib.write(" bus(ADDR){\n")
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self.lib.write(" bus_type : ADDR; \n")
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self.lib.write(" direction : input; \n")
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self.lib.write(" capacitance : {0}; \n".format(tech.spice["FF_in_cap"]))
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self.lib.write(" max_transition : {0};\n".format(self.slews[-1]))
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self.lib.write(" fanout_load : 1.000000;\n")
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self.lib.write(" pin(ADDR[{0}:0])".format(self.addr_size - 1))
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self.lib.write("{\n")
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self.write_FF_setuphold()
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self.lib.write(" }\n")
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self.lib.write(" }\n\n")
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def write_control_pins(self):
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""" Adds control pins timing results."""
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ctrl_pin_names = ["CSb", "OEb", "WEb"]
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for i in ctrl_pin_names:
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self.lib.write(" pin({0})".format(i))
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self.lib.write("{\n")
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self.lib.write(" direction : input; \n")
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self.lib.write(" capacitance : {0}; \n".format(tech.spice["FF_in_cap"]))
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self.write_FF_setuphold()
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self.lib.write(" }\n\n")
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def write_clk(self):
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""" Adds clk pin timing results."""
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self.compute_delay()
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self.lib.write(" pin(clk){\n")
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self.lib.write(" clock : true;\n")
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self.lib.write(" direction : input; \n")
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self.lib.write(" capacitance : {0}; \n".format(tech.spice["FF_in_cap"]))
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min_pulse_width = ch.round_time(self.delay["min_period"])/2.0
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min_period = ch.round_time(self.delay["min_period"])
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self.lib.write(" timing(){ \n")
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self.lib.write(" timing_type :\"min_pulse_width\"; \n")
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self.lib.write(" related_pin : clk; \n")
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self.lib.write(" rise_constraint(scalar) {\n")
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self.lib.write(" values(\"{0}\"); \n".format(min_pulse_width))
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self.lib.write(" }\n")
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self.lib.write(" fall_constraint(scalar) {\n")
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self.lib.write(" values(\"{0}\"); \n".format(min_pulse_width))
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self.lib.write(" }\n")
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self.lib.write(" }\n")
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self.lib.write(" timing(){ \n")
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self.lib.write(" timing_type :\"minimum_period\"; \n")
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self.lib.write(" related_pin : clk; \n")
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self.lib.write(" rise_constraint(scalar) {\n")
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self.lib.write(" values(\"{0}\"); \n".format(min_period))
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self.lib.write(" }\n")
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self.lib.write(" fall_constraint(scalar) {\n")
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self.lib.write(" values(\"{0}\"); \n".format(min_period))
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self.lib.write(" }\n")
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self.lib.write(" }\n")
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self.lib.write(" }\n")
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self.lib.write(" }\n")
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self.lib.write("}\n")
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def compute_delay(self):
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""" Do the analysis if we haven't characterized the SRAM yet """
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try:
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self.d
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except AttributeError:
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self.d = delay.delay(self.sram, self.sim_sp_file)
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if self.use_model:
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self.delay = self.d.analytical_model(self.sram,self.slews,self.loads)
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else:
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probe_address = "1" * self.addr_size
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probe_data = self.word_size - 1
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# We must trim based on a specific address and data bit
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if OPTS.trim_netlist:
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self.trimsp.trim(probe_address,probe_data)
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self.delay = self.d.analyze(probe_address, probe_data, self.slews, self.loads)
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def compute_setup_hold(self):
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""" Do the analysis if we haven't characterized a FF yet """
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# Do the analysis if we haven't characterized a FF yet
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try:
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self.sh
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except AttributeError:
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self.sh = setup_hold.setup_hold()
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if self.use_model:
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self.times = self.sh.analytical_model(self.slews,self.loads)
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else:
|
|
self.times = self.sh.analyze(self.slews,self.slews)
|
|
|