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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
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01fe02bd90f986ec7ec60a5b936494dca397dfe4
OpenRAM/compiler/characterizer
T
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mrg 9fe6358569 Change .spinit to .spiceinit
2020-10-05 13:50:04 -07:00
..
__init__.py
Removed unused characterization module.
2019-07-30 20:33:17 -07:00
bit_polarity.py
Clean up. Split class into own file.
2019-07-24 08:15:10 -07:00
charutils.py
Clean up. Split class into own file.
2019-07-24 08:15:10 -07:00
delay.py
Initial pex sram test.
2020-10-02 13:32:52 -07:00
functional.py
Initial pex sram test.
2020-10-02 13:32:52 -07:00
lib.py
Make drc and lvs errors a member variable. Run only once.
2020-07-13 12:49:24 -07:00
logical_effort.py
Made all cin function relate to farads and all input_load relate to relative units.
2019-08-08 01:57:04 -07:00
measurements.py
Undo super() in measurement abstract class
2020-08-12 12:10:12 -07:00
model_check.py
Change inheritance inits to use super
2020-08-06 11:33:26 -07:00
setup_hold.py
Remove extra print
2019-11-17 10:40:01 -08:00
simulation.py
PEP8 cleanup. Un-hard-code bitcell layers. Remove dead variable.
2020-10-01 11:10:18 -07:00
sram_op.py
Clean up. Split class into own file.
2019-07-24 08:15:10 -07:00
stimuli.py
Change .spinit to .spiceinit
2020-10-05 13:50:04 -07:00
trim_spice.py
Characterization for extra rows
2020-02-20 17:01:52 +00:00
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