mirror of https://github.com/VLSIDA/OpenRAM.git
286 lines
11 KiB
Python
286 lines
11 KiB
Python
import debug
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import re
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import os
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import math
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import verilog
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class spice(verilog.verilog):
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"""
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This provides a set of useful generic types for hierarchy
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management. If a module is a custom designed cell, it will read from
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the GDS and spice files and perform LVS/DRC. If it is dynamically
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generated, it should implement a constructor to create the
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layout/netlist and perform LVS/DRC.
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Class consisting of a set of modules and instances of these modules
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"""
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def __init__(self, name):
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self.name = name
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self.mods = [] # Holds subckts/mods for this module
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self.pins = [] # Holds the pins for this module
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self.pin_type = {} # The type map of each pin: INPUT, OUTPUT, INOUT, POWER, GROUND
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# for each instance, this is the set of nets/nodes that map to the pins for this instance
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# THIS MUST MATCH THE ORDER OF THE PINS (restriction imposed by the
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# Spice format)
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self.conns = []
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self.sp_read()
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############################################################
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# Spice circuit
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############################################################
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def add_pin(self, name, pin_type="INOUT"):
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""" Adds a pin to the pins list. Default type is INOUT signal. """
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self.pins.append(name)
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self.pin_type[name]=pin_type
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def add_pin_list(self, pin_list, pin_type_list="INOUT"):
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""" Adds a pin_list to the pins list """
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# The type list can be a single type for all pins
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# or a list that is the same length as the pin list.
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if type(pin_type_list)==str:
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for pin in pin_list:
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self.add_pin(pin,pin_type_list)
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elif len(pin_type_list)==len(pin_list):
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for (pin,ptype) in zip(pin_list, pin_type_list):
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self.add_pin(pin,ptype)
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else:
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debug.error("Mismatch in type and pin list lengths.", -1)
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def get_pin_type(self, name):
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""" Returns the type of the signal pin. """
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return self.pin_type[name]
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def get_pin_dir(self, name):
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""" Returns the direction of the pin. (Supply/ground are INOUT). """
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if self.pin_type[name] in ["POWER","GROUND"]:
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return "INOUT"
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else:
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return self.pin_type[name]
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def add_mod(self, mod):
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"""Adds a subckt/submodule to the subckt hierarchy"""
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self.mods.append(mod)
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def connect_inst(self, args, check=True):
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"""Connects the pins of the last instance added
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It is preferred to use the function with the check to find if
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there is a problem. The check option can be set to false
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where we dynamically generate groups of connections after a
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group of modules are generated."""
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if (check and (len(self.insts[-1].mod.pins) != len(args))):
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debug.error("Number of net connections ({0}) does not match last instance ({1})".format(len(self.insts[-1].mod.pins),
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len(args)), 1)
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self.conns.append(args)
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if check and (len(self.insts)!=len(self.conns)):
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debug.error("{0} : Not all instance pins ({1}) are connected ({2}).".format(self.name,
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len(self.insts),
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len(self.conns)))
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debug.error("Instances: \n"+str(self.insts))
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debug.error("-----")
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debug.error("Connections: \n"+str(self.conns),1)
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def sp_read(self):
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"""Reads the sp file (and parse the pins) from the library
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Otherwise, initialize it to null for dynamic generation"""
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if os.path.isfile(self.sp_file):
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debug.info(3, "opening {0}".format(self.sp_file))
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f = open(self.sp_file)
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self.spice = f.readlines()
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for i in range(len(self.spice)):
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self.spice[i] = self.spice[i].rstrip(" \n")
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# find first subckt line in the file
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subckt = re.compile("^.subckt", re.IGNORECASE)
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subckt_line = filter(subckt.search, self.spice)[0]
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# parses line into ports and remove subckt
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self.pins = subckt_line.split(" ")[2:]
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else:
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self.spice = []
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def contains(self, mod, modlist):
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for x in modlist:
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if x.name == mod.name:
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return True
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return False
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def sp_write_file(self, sp, usedMODS):
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""" Recursive spice subcircuit write;
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Writes the spice subcircuit from the library or the dynamically generated one"""
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if not self.spice:
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# recursively write the modules
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for i in self.mods:
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if self.contains(i, usedMODS):
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continue
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usedMODS.append(i)
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i.sp_write_file(sp, usedMODS)
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if len(self.insts) == 0:
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return
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if self.pins == []:
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return
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# write out the first spice line (the subcircuit)
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sp.write("\n.SUBCKT {0} {1}\n".format(self.name,
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" ".join(self.pins)))
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# every instance must have a set of connections, even if it is empty.
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if len(self.insts)!=len(self.conns):
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debug.error("{0} : Not all instance pins ({1}) are connected ({2}).".format(self.name,
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len(self.insts),
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len(self.conns)))
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debug.error("Instances: \n"+str(self.insts))
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debug.error("-----")
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debug.error("Connections: \n"+str(self.conns),1)
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for i in range(len(self.insts)):
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# we don't need to output connections of empty instances.
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# these are wires and paths
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if self.conns[i] == []:
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continue
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if hasattr(self.insts[i].mod,"spice_device"):
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sp.write(self.insts[i].mod.spice_device.format(self.insts[i].name,
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" ".join(self.conns[i])))
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sp.write("\n")
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else:
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sp.write("X{0} {1} {2}\n".format(self.insts[i].name,
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" ".join(self.conns[i]),
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self.insts[i].mod.name))
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sp.write(".ENDS {0}\n".format(self.name))
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else:
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# write the subcircuit itself
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# Including the file path makes the unit test fail for other users.
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#if os.path.isfile(self.sp_file):
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# sp.write("\n* {0}\n".format(self.sp_file))
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sp.write("\n".join(self.spice))
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sp.write("\n")
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def sp_write(self, spname):
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"""Writes the spice to files"""
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debug.info(3, "Writing to {0}".format(spname))
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spfile = open(spname, 'w')
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spfile.write("*FIRST LINE IS A COMMENT\n")
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usedMODS = list()
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self.sp_write_file(spfile, usedMODS)
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del usedMODS
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spfile.close()
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def analytical_delay(self, slew, load=0.0):
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"""Inform users undefined delay module while building new modules"""
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debug.warning("Design Class {0} delay function needs to be defined"
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.format(self.__class__.__name__))
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debug.warning("Class {0} name {1}"
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.format(self.__class__.__name__,
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self.name))
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# return 0 to keep code running while building
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return delay_data(0.0, 0.0)
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def cal_delay_with_rc(self, r, c ,slew, swing = 0.5):
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"""
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Calculate the delay of a mosfet by
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modeling it as a resistance driving a capacitance
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"""
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swing_factor = abs(math.log(1-swing)) # time constant based on swing
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delay = swing_factor * r * c #c is in ff and delay is in fs
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delay = delay * 0.001 #make the unit to ps
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# Output slew should be linear to input slew which is described
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# as 0.005* slew.
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# The slew will be also influenced by the delay.
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# If no input slew(or too small to make impact)
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# The mimum slew should be the time to charge RC.
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# Delay * 2 is from 0 to 100% swing. 0.6*2*delay is from 20%-80%.
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slew = delay * 0.6 * 2 + 0.005 * slew
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return delay_data(delay = delay, slew = slew)
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def return_delay(self, delay, slew):
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return delay_data(delay, slew)
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def generate_rc_net(self,lump_num, wire_length, wire_width):
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return wire_spice_model(lump_num, wire_length, wire_width)
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class delay_data:
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"""
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This is the delay class to represent the delay information
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Time is 50% of the signal to 50% of reference signal delay.
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Slew is the 10% of the signal to 90% of signal
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"""
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def __init__(self, delay=0.0, slew=0.0):
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""" init function support two init method"""
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# will take single input as a coordinate
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self.delay = delay
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self.slew = slew
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def __str__(self):
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""" override print function output """
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return "Delay Data: Delay "+str(self.delay)+", Slew "+str(self.slew)+""
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def __add__(self, other):
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"""
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Override - function (left), for delay_data: a+b != b+a
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"""
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assert isinstance(other,delay_data)
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return delay_data(other.delay + self.delay,
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other.slew)
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def __radd__(self, other):
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"""
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Override - function (right), for delay_data: a+b != b+a
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"""
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assert isinstance(other,delay_data)
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return delay_data(other.delay + self.delay,
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self.slew)
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class wire_spice_model:
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"""
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This is the spice class to represent a wire
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"""
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def __init__(self, lump_num, wire_length, wire_width):
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self.lump_num = lump_num # the number of segment the wire delay has
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self.wire_c = self.cal_wire_c(wire_length, wire_width) # c in each segment
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self.wire_r = self.cal_wire_r(wire_length, wire_width) # r in each segment
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def cal_wire_c(self, wire_length, wire_width):
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from tech import spice
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total_c = spice["wire_unit_c"] * wire_length * wire_width
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wire_c = total_c / self.lump_num
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return wire_c
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def cal_wire_r(self, wire_length, wire_width):
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from tech import spice
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total_r = spice["wire_unit_r"] * wire_length / wire_width
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wire_r = total_r / self.lump_num
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return wire_r
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def return_input_cap(self):
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return 0.5 * self.wire_c * self.lump_num
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def return_delay_over_wire(self, slew, swing = 0.5):
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# delay will be sum of arithmetic sequence start from
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# rc to self.lump_num*rc with step of rc
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swing_factor = abs(math.log(1-swing)) # time constant based on swing
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sum_factor = (1+self.lump_num) * self.lump_num * 0.5 # sum of the arithmetic sequence
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delay = sum_factor * swing_factor * self.wire_r * self.wire_c
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slew = delay * 2 + slew
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result= delay_data(delay, slew)
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return result
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