mirror of https://github.com/VLSIDA/OpenRAM.git
this is technology specific database to store data about the custom design cells. For now it only contains on which axis the bitcells are mirrored. This is a first step to support thin cells that need to be mirrored on the x and y axis. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> |
||
|---|---|---|
| .. | ||
| README | ||
| SCN3ME_SUBM.30.tech | ||
| __init__.py | ||
| calibreDRC_scn3me_subm.rul | ||
| calibreLVS_scn3me_subm.rul | ||
| tech.py | ||
README
The file SCN3ME_SUBM.30.tech is from qflow 1.2 and has the following license information: --------------------------------------------------------------- Tim Edwards Open Circuit Design v1.0 April 2013 v1.1 May 2015 v1.2 April 2017 --------------------------------------------------------------- GPL Copyright (c) 2017