mirror of https://github.com/VLSIDA/OpenRAM.git
123 lines
4.4 KiB
Python
123 lines
4.4 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2024 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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from openram import debug
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from openram.base import design
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from openram.base import vector
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from openram.sram_factory import factory
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from openram.tech import drc
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from openram import OPTS
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class tri_gate_array(design):
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"""
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Dynamically generated tri gate array of all bitlines. words_per_row
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"""
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def __init__(self, columns, word_size, name):
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"""Intial function of tri gate array """
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super().__init__(name)
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debug.info(1, "Creating {0}".format(self.name))
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self.columns = columns
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self.word_size = word_size
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self.words_per_row = int(self.columns / self.word_size)
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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self.add_modules()
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self.add_pins()
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self.create_array()
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def create_layout(self):
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self.width = (self.columns / self.words_per_row) * self.tri.width
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self.height = self.tri.height
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self.place_array()
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self.add_layout_pins()
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self.add_boundary()
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self.DRC_LVS()
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def add_modules(self):
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self.tri = factory.create(module_type="tri_gate")
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def add_pins(self):
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"""create the name of pins depend on the word size"""
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for i in range(self.word_size):
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self.add_pin("in_{0}".format(i))
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for i in range(self.word_size):
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self.add_pin("out_{0}".format(i))
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for pin in ["en", "en_bar", "vdd", "gnd"]:
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self.add_pin(pin)
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def create_array(self):
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"""add tri gate to the array """
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self.tri_inst = {}
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for i in range(0,self.columns,self.words_per_row):
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name = "Xtri_gate{0}".format(i)
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self.tri_inst[i]=self.add_inst(name=name,
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mod=self.tri)
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index = int(i/self.words_per_row)
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self.connect_inst(["in_{0}".format(index),
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"out_{0}".format(index),
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"en", "en_bar", "vdd", "gnd"])
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def place_array(self):
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""" Place the tri gate to the array """
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for i in range(0,self.columns,self.words_per_row):
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base = vector(i*self.tri.width, 0)
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self.tri_inst[i].place(base)
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def add_layout_pins(self):
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for i in range(0,self.columns,self.words_per_row):
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index = int(i/self.words_per_row)
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in_pin = self.tri_inst[i].get_pin("in")
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self.add_layout_pin(text="in_{0}".format(index),
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layer="m2",
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offset=in_pin.ll(),
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width=in_pin.width(),
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height=in_pin.height())
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out_pin = self.tri_inst[i].get_pin("out")
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self.add_layout_pin(text="out_{0}".format(index),
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layer="m2",
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offset=out_pin.ll(),
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width=out_pin.width(),
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height=out_pin.height())
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# Route both supplies
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for n in ["vdd", "gnd"]:
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for supply_pin in self.tri_inst[i].get_pins(n):
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pin_pos = supply_pin.center()
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self.add_via_center(layers=self.m2_stack,
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offset=pin_pos)
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self.add_layout_pin_rect_center(text=n,
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layer="m3",
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offset=pin_pos)
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width = self.tri.width * self.columns - (self.words_per_row - 1) * self.tri.width
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en_pin = self.tri_inst[0].get_pin("en")
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self.add_layout_pin(text="en",
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layer="m1",
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offset=en_pin.ll().scale(0, 1),
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width=width,
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height=drc("minwidth_m1"))
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enbar_pin = self.tri_inst[0].get_pin("en_bar")
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self.add_layout_pin(text="en_bar",
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layer="m1",
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offset=enbar_pin.ll().scale(0, 1),
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width=width,
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height=drc("minwidth_m1"))
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