mirror of https://github.com/VLSIDA/OpenRAM.git
363 lines
16 KiB
Python
363 lines
16 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2024 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import operator
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from math import ceil
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from openram import debug
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from openram.base import vector
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from openram.base import logical_effort
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from openram.base.utils import round_to_grid
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from openram.base.errors import drc_error
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from openram.sram_factory import factory
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from openram.tech import drc, parameter, spice
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from openram.tech import cell_properties as cell_props
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from openram import OPTS
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from .pgate import *
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class pinv(pgate):
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"""
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Pinv generates gds of a parametrically sized inverter. The
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size is specified as the drive size (relative to minimum NMOS) and
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a beta value for choosing the pmos size. The inverter's cell
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height is usually the same as the 6t library cell and is measured
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from center of rail to rail.
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"""
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# binning %error tracker
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bin_count = 0
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bin_error = 0
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def __init__(self, name, size=1, beta=parameter["beta"], height=None, add_wells=True):
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debug.info(2,
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"creating pinv structure {0} with size of {1}".format(name,
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size))
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self.add_comment("size: {}".format(size))
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self.size = size
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debug.check(self.size >= 1, "Must have a size greater than or equal to 1.")
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self.nmos_size = size
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self.pmos_size = beta * size
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self.beta = beta
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super().__init__(name, height, add_wells)
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def create_netlist(self):
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""" Calls all functions related to the generation of the netlist """
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self.add_pins()
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self.determine_tx_mults()
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self.add_ptx()
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self.create_ptx()
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def create_layout(self):
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""" Calls all functions related to the generation of the layout """
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self.place_ptx()
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if self.add_wells:
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self.add_well_contacts()
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self.determine_width()
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self.extend_wells()
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self.route_input_gate(self.pmos_inst,
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self.nmos_inst,
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self.output_pos.y,
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"A",
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position="farleft")
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self.route_outputs()
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self.route_supply_rails()
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self.connect_rails()
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self.add_boundary()
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def add_pins(self):
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""" Adds pins for spice netlist """
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pin_list = ["A", "Z", "vdd", "gnd"]
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dir_list = ["INPUT", "OUTPUT", "POWER", "GROUND"]
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self.add_pin_list(pin_list, dir_list)
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def determine_tx_mults(self):
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"""
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Determines the number of fingers needed to achieve the size within
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the height constraint. This may fail if the user has a tight height.
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"""
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# This may make the result differ when the layout is created...
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if OPTS.netlist_only:
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self.tx_mults = 1
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self.nmos_width = self.nmos_size * drc("minwidth_tx")
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self.pmos_width = self.pmos_size * drc("minwidth_tx")
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if cell_props.ptx.bin_spice_models:
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(self.nmos_width, self.tx_mults) = pgate.best_bin("nmos", self.nmos_width)
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(self.pmos_width, self.tx_mults) = pgate.best_bin("pmos", self.pmos_width)
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return
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# Do a quick sanity check and bail if unlikely feasible height
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# Sanity check. can we make an inverter in the height
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# with minimum tx sizes?
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# Assume we need 3 metal 1 pitches (2 power rails, one
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# between the tx for the drain)
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# plus the tx height
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nmos = factory.create(module_type="ptx",
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tx_type="nmos")
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pmos = factory.create(module_type="ptx",
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width=drc("minwidth_tx"),
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tx_type="pmos")
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tx_height = nmos.poly_height + pmos.poly_height
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# rotated m1 pitch or poly to active spacing
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min_channel = max(self.poly_contact.width + self.m1_space,
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self.poly_contact.width + 2 * self.poly_to_active)
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total_height = tx_height + min_channel + 2 * self.top_bottom_space
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# debug.check(self.height > total_height,
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# "Cell height {0} too small for simple min height {1}.".format(self.height,
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# total_height))
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if total_height > self.height:
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msg = "Cell height {0} too small for simple min height {1}.".format(self.height, total_height)
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raise drc_error(msg)
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# Determine the height left to the transistors to determine
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# the number of fingers
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tx_height_available = self.height - min_channel - 2 * self.top_bottom_space
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# Divide the height in half. Could divide proportional to beta,
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# but this makes connecting wells of multiple cells easier.
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# Subtract the poly space under the rail of the tx
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nmos_height_available = 0.5 * tx_height_available - 0.5 * self.poly_space
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pmos_height_available = 0.5 * tx_height_available - 0.5 * self.poly_space
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debug.info(2,
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"Height avail {0:.4f} PMOS {1:.4f} NMOS {2:.4f}".format(tx_height_available,
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nmos_height_available,
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pmos_height_available))
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# Determine the number of mults for each to fit width
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# into available space
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if not cell_props.ptx.bin_spice_models:
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self.nmos_width = self.nmos_size * drc("minwidth_tx")
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self.pmos_width = self.pmos_size * drc("minwidth_tx")
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nmos_required_mults = max(int(ceil(self.nmos_width / nmos_height_available)), 1)
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pmos_required_mults = max(int(ceil(self.pmos_width / pmos_height_available)), 1)
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# The mults must be the same for easy connection of poly
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self.tx_mults = max(nmos_required_mults, pmos_required_mults)
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# Recompute each mult width and check it isn't too small
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# This could happen if the height is narrow and the size is small
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# User should pick a bigger size to fix it...
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# We also need to round the width to the grid or we will end up
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# with LVS property mismatch errors when fingers are not a grid
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# length and get rounded in the offset geometry.
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self.nmos_width = round_to_grid(self.nmos_width / self.tx_mults)
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# debug.check(self.nmos_width >= drc("minwidth_tx"),
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# "Cannot finger NMOS transistors to fit cell height.")
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if self.nmos_width < drc("minwidth_tx"):
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raise drc_error("Cannot finger NMOS transistors to fit cell height.")
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self.pmos_width = round_to_grid(self.pmos_width / self.tx_mults)
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#debug.check(self.pmos_width >= drc("minwidth_tx"),
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# "Cannot finger PMOS transistors to fit cell height.")
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if self.pmos_width < drc("minwidth_tx"):
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raise drc_error("Cannot finger NMOS transistors to fit cell height.")
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else:
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self.nmos_width = self.nmos_size * drc("minwidth_tx")
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self.pmos_width = self.pmos_size * drc("minwidth_tx")
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nmos_bins = self.scaled_bins("nmos", self.nmos_width)
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pmos_bins = self.scaled_bins("pmos", self.pmos_width)
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valid_pmos = []
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for bin in pmos_bins:
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if abs(self.bin_accuracy(self.pmos_width, bin[0])) > OPTS.accuracy_requirement and abs(self.bin_accuracy(self.pmos_width, bin[0])) <= 1:
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valid_pmos.append(bin)
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valid_pmos.sort(key = operator.itemgetter(1))
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valid_nmos = []
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for bin in nmos_bins:
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if abs(self.bin_accuracy(self.nmos_width, bin[0])) > OPTS.accuracy_requirement and abs(self.bin_accuracy(self.nmos_width, bin[0])) <= 1:
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valid_nmos.append(bin)
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valid_nmos.sort(key = operator.itemgetter(1))
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for bin in valid_pmos:
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if bin[0]/bin[1] < pmos_height_available:
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self.pmos_width = bin[0]/bin[1]
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pmos_mults = bin[1]
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break
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for bin in valid_nmos:
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if bin[0]/bin[1] < nmos_height_available:
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self.nmos_width = bin[0]/bin[1]
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nmos_mults = bin[1]
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break
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self.tx_mults = max(pmos_mults, nmos_mults)
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debug.info(2, "prebinning {0} tx, target: {4}, found {1} x {2} = {3}".format("pmos", self.pmos_width, pmos_mults, self.pmos_width * pmos_mults, self.pmos_size * drc("minwidth_tx")))
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debug.info(2, "prebinning {0} tx, target: {4}, found {1} x {2} = {3}".format("nmos", self.nmos_width, nmos_mults, self.nmos_width * nmos_mults, self.nmos_size * drc("minwidth_tx")))
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pinv.bin_count += 1
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pinv.bin_error += abs(((self.pmos_width * pmos_mults) - (self.pmos_size * drc("minwidth_tx")))/(self.pmos_size * drc("minwidth_tx")))
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pinv.bin_count += 1
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pinv.bin_error += abs(((self.nmos_width * nmos_mults) - (self.nmos_size * drc("minwidth_tx")))/(self.nmos_size * drc("minwidth_tx")))
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debug.info(2, "pinv bin count: {0} pinv bin error: {1} percent error {2}".format(pinv.bin_count, pinv.bin_error, pinv.bin_error/pinv.bin_count))
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def add_ptx(self):
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""" Create the PMOS and NMOS transistors. """
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self.nmos = factory.create(module_type="ptx",
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width=self.nmos_width,
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mults=self.tx_mults,
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tx_type="nmos",
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add_source_contact=self.route_layer,
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add_drain_contact=self.route_layer,
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connect_poly=True,
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connect_drain_active=True)
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self.pmos = factory.create(module_type="ptx",
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width=self.pmos_width,
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mults=self.tx_mults,
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tx_type="pmos",
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add_source_contact=self.route_layer,
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add_drain_contact=self.route_layer,
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connect_poly=True,
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connect_drain_active=True)
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def create_ptx(self):
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"""
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Create the PMOS and NMOS netlist.
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"""
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self.pmos_inst = self.add_inst(name="pinv_pmos",
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mod=self.pmos)
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self.connect_inst(["Z", "A", "vdd", "vdd"])
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self.nmos_inst = self.add_inst(name="pinv_nmos",
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mod=self.nmos)
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self.connect_inst(["Z", "A", "gnd", "gnd"])
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def place_ptx(self):
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"""
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Place PMOS and NMOS to the layout at the upper-most and lowest position
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to provide maximum routing in channel
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"""
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# place PMOS so it is half a poly spacing down from the top
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self.pmos_pos = self.pmos.active_offset.scale(1, 0) \
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+ vector(0,
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self.height - self.pmos.active_height - self.top_bottom_space)
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self.pmos_inst.place(self.pmos_pos)
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# place NMOS so that it is half a poly spacing up from the bottom
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self.nmos_pos = self.nmos.active_offset.scale(1, 0) \
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+ vector(0, self.top_bottom_space)
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self.nmos_inst.place(self.nmos_pos)
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# Output position will be in between the PMOS and NMOS drains
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pmos_drain_pos = self.pmos_inst.get_pin("D").ll()
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nmos_drain_pos = self.nmos_inst.get_pin("D").ul()
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self.output_pos = vector(0, 0.5 * (pmos_drain_pos.y + nmos_drain_pos.y))
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def route_outputs(self):
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"""
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Route the output (drains) together.
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Optionally, routes output to edge.
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"""
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# Get the drain pins
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nmos_drain_pin = self.nmos_inst.get_pin("D")
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pmos_drain_pin = self.pmos_inst.get_pin("D")
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# Pick point at right most of NMOS and connect down to PMOS
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nmos_drain_pos = nmos_drain_pin.bc()
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pmos_drain_pos = vector(nmos_drain_pos.x, pmos_drain_pin.uc().y)
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self.add_path(self.route_layer, [nmos_drain_pos, pmos_drain_pos])
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# Remember the mid for the output
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mid_drain_offset = vector(nmos_drain_pos.x, self.output_pos.y)
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# This leaves the output as an internal pin (min sized)
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output_offset = mid_drain_offset + vector(0.5 * self.route_layer_width, 0)
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self.add_layout_pin_rect_center(text="Z",
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layer=self.route_layer,
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offset=output_offset)
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def add_well_contacts(self):
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""" Add n/p well taps to the layout and connect to supplies """
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self.add_nwell_contact(self.pmos, self.pmos_pos)
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self.add_pwell_contact(self.nmos, self.nmos_pos)
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def connect_rails(self):
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""" Connect the nmos and pmos to its respective power rails """
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self.connect_pin_to_rail(self.nmos_inst, "S", "gnd")
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self.connect_pin_to_rail(self.pmos_inst, "S", "vdd")
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def analytical_power(self, corner, load):
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"""Returns dynamic and leakage power. Results in nW"""
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c_eff = self.calculate_effective_capacitance(load)
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freq = spice["default_event_frequency"]
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power_dyn = self.calc_dynamic_power(corner, c_eff, freq)
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power_leak = spice["inv_leakage"]
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total_power = self.return_power(power_dyn, power_leak)
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return total_power
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def calculate_effective_capacitance(self, load):
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"""Computes effective capacitance. Results in fF"""
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c_load = load
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# In fF
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c_para = spice["min_tx_drain_c"] * (self.nmos_size / parameter["min_tx_size"])
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transition_prob = 0.5
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return transition_prob * (c_load + c_para)
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def input_load(self):
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"""
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Return the relative capacitance of the gate connection in generic capacitive
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units relative to the minimum width of a transistor
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"""
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return self.nmos_size + self.pmos_size
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def get_stage_effort(self, cout, inp_is_rise=True):
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"""
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Returns an object representing the parameters for delay in tau units.
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Optional is_rise refers to the input direction rise/fall.
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Input inverted by this stage.
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"""
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parasitic_delay = 1
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return logical_effort(self.name,
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self.size,
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self.input_load(),
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cout,
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parasitic_delay,
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not inp_is_rise)
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def build_graph(self, graph, inst_name, port_nets):
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"""
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Adds edges based on inputs/outputs.
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Overrides base class function.
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"""
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self.add_graph_edges(graph, port_nets)
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def is_non_inverting(self):
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"""Return input to output polarity for module"""
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return False
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def get_on_resistance(self):
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"""On resistance of pinv, defined by single nmos"""
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is_nchannel = True
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stack = 1
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is_cell = False
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return self.tr_r_on(self.nmos_width, is_nchannel, stack, is_cell)
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def get_input_capacitance(self):
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"""Input cap of input, passes width of gates to gate cap function"""
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return self.gate_c(self.nmos_width+self.pmos_width)
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def get_intrinsic_capacitance(self):
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"""Get the drain capacitances of the TXs in the gate."""
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nmos_stack = 1
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nmos_drain_c = self.drain_c_(self.nmos_width*self.tx_mults,
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nmos_stack,
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self.tx_mults)
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pmos_drain_c = self.drain_c_(self.pmos_width*self.tx_mults,
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1,
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self.tx_mults)
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return nmos_drain_c + pmos_drain_c
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