mirror of https://github.com/VLSIDA/OpenRAM.git
167 lines
6.6 KiB
Python
167 lines
6.6 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2024 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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from openram import debug
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from openram.base import design
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from openram.base import vector
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from openram.sram_factory import factory
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from openram import OPTS
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class dff_array(design):
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"""
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This is a simple row (or multiple rows) of flops.
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Unlike the data flops, these are never spaced out.
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"""
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def __init__(self, rows, columns, name=""):
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self.rows = rows
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self.columns = columns
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if name=="":
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name = "dff_array_{0}x{1}".format(rows, columns)
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super().__init__(name)
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debug.info(1, "Creating {0} rows={1} cols={2}".format(self.name, self.rows, self.columns))
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self.add_comment("rows: {0} cols: {1}".format(rows, columns))
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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self.add_modules()
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self.add_pins()
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self.create_dff_array()
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def create_layout(self):
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self.width = self.columns * self.dff.width
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self.height = self.rows * self.dff.height
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self.place_dff_array()
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self.route_supplies()
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self.add_layout_pins()
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self.add_boundary()
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self.DRC_LVS()
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def add_modules(self):
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self.dff = factory.create(module_type="dff")
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def add_pins(self):
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for row in range(self.rows):
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for col in range(self.columns):
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self.add_pin(self.get_din_name(row, col), "INPUT")
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for row in range(self.rows):
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for col in range(self.columns):
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self.add_pin(self.get_dout_name(row, col), "OUTPUT")
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self.add_pin("clk", "INPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def create_dff_array(self):
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self.dff_insts={}
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for row in range(self.rows):
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for col in range(self.columns):
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name = "dff_r{0}_c{1}".format(row, col)
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self.dff_insts[row, col]=self.add_inst(name=name,
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mod=self.dff)
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instance_ports = [self.get_din_name(row, col),
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self.get_dout_name(row, col)]
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for port in self.dff.pins:
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if port != 'D' and port != 'Q':
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instance_ports.append(port)
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self.connect_inst(instance_ports)
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def place_dff_array(self):
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for row in range(self.rows):
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for col in range(self.columns):
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if (row % 2 == 0):
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base = vector(col * self.dff.width, row * self.dff.height)
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mirror = "R0"
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else:
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base = vector(col * self.dff.width, (row + 1) * self.dff.height)
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mirror = "MX"
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self.dff_insts[row, col].place(offset=base,
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mirror=mirror)
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def get_din_name(self, row, col):
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if self.columns == 1:
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din_name = "din_{0}".format(row)
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elif self.rows == 1:
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din_name = "din_{0}".format(col)
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else:
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din_name = "din_{0}_{1}".format(row, col)
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return din_name
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def get_dout_name(self, row, col):
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if self.columns == 1:
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dout_name = "dout_{0}".format(row)
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elif self.rows == 1:
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dout_name = "dout_{0}".format(col)
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else:
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dout_name = "dout_{0}_{1}".format(row, col)
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return dout_name
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def route_supplies(self):
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if self.rows > 1:
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# Vertical straps on ends if multiple rows
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left_dff_insts = [self.dff_insts[x, 0] for x in range(self.rows)]
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right_dff_insts = [self.dff_insts[x, self.columns-1] for x in range(self.rows)]
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self.route_vertical_pins("vdd", left_dff_insts, xside="lx", yside="cy")
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self.route_vertical_pins("gnd", right_dff_insts, xside="rx", yside="cy")
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else:
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# Add connections every 4 cells
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for col in range(0, self.columns, 4):
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vdd_pin=self.dff_insts[0, col].get_pin("vdd")
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self.add_power_pin("vdd", vdd_pin.lc(), start_layer=vdd_pin.layer)
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# Add connections every 4 cells
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for col in range(0, self.columns, 4):
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gnd_pin=self.dff_insts[0, col].get_pin("gnd")
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self.add_power_pin("gnd", gnd_pin.rc(), start_layer=gnd_pin.layer)
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def add_layout_pins(self):
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for row in range(self.rows):
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for col in range(self.columns):
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din_pin = self.dff_insts[row, col].get_pin("D")
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debug.check(din_pin.layer == "m2", "DFF D pin not on metal2")
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self.add_layout_pin(text=self.get_din_name(row, col),
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layer=din_pin.layer,
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offset=din_pin.ll(),
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width=din_pin.width(),
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height=din_pin.height())
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dout_pin = self.dff_insts[row, col].get_pin("Q")
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debug.check(dout_pin.layer == "m2", "DFF Q pin not on metal2")
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self.add_layout_pin(text=self.get_dout_name(row, col),
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layer=dout_pin.layer,
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offset=dout_pin.ll(),
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width=dout_pin.width(),
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height=dout_pin.height())
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# Create vertical spines to a single horizontal rail
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clk_pin = self.dff_insts[0, 0].get_pin("clk")
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clk_ypos = 2 * self.m3_pitch + self.m3_width
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debug.check(clk_pin.layer == "m2", "DFF clk pin not on metal2")
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self.add_layout_pin_segment_center(text="clk",
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layer="m3",
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start=vector(0, clk_ypos),
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end=vector(self.width, clk_ypos))
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for col in range(self.columns):
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clk_pin = self.dff_insts[0, col].get_pin("clk")
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# Make a vertical strip for each column
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self.add_rect(layer="m2",
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offset=clk_pin.ll().scale(1, 0),
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width=self.m2_width,
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height=self.height)
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# Drop a via to the M3 pin
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self.add_via_stack_center(from_layer=clk_pin.layer,
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to_layer="m3",
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offset=vector(clk_pin.cx(), clk_ypos))
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