mirror of https://github.com/VLSIDA/OpenRAM.git
744 lines
33 KiB
Python
744 lines
33 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2021 Regents of the University of California
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# All rights reserved.
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#
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import debug
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from base import vector
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from base import contact
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from .bitcell_base_array import bitcell_base_array
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from tech import drc, spice
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from tech import cell_properties as props
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from globals import OPTS
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from sram_factory import factory
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class replica_bitcell_array(bitcell_base_array):
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"""
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Creates a bitcell arrow of cols x rows and then adds the replica
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and dummy columns and rows. Replica columns are on the left and
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right, respectively and connected to the given bitcell ports.
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Dummy are the outside columns/rows with WL and BL tied to gnd.
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Requires a regular bitcell array, replica bitcell, and dummy
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bitcell (Bl/BR disconnected).
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"""
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def __init__(self, rows, cols, rbl=None, left_rbl=None, right_rbl=None, name=""):
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super().__init__(name, rows, cols, column_offset=0)
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debug.info(1, "Creating {0} {1} x {2} rbls: {3} left_rbl: {4} right_rbl: {5}".format(self.name,
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rows,
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cols,
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rbl,
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left_rbl,
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right_rbl))
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self.add_comment("rows: {0} cols: {1}".format(rows, cols))
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self.add_comment("rbl: {0} left_rbl: {1} right_rbl: {2}".format(rbl, left_rbl, right_rbl))
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self.column_size = cols
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self.row_size = rows
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# This is how many RBLs are in all the arrays
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if rbl:
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self.rbl = rbl
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else:
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self.rbl=[1, 1 if len(self.all_ports)>1 else 0]
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# This specifies which RBL to put on the left or right
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# by port number
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# This could be an empty list
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if left_rbl != None:
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self.left_rbl = left_rbl
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else:
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self.left_rbl = [0]
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# This could be an empty list
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if right_rbl != None:
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self.right_rbl = right_rbl
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else:
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self.right_rbl=[1] if len(self.all_ports) > 1 else []
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self.rbls = self.left_rbl + self.right_rbl
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debug.check(sum(self.rbl) == len(self.all_ports),
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"Invalid number of RBLs for port configuration.")
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debug.check(sum(self.rbl) >= len(self.left_rbl) + len(self.right_rbl),
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"Invalid number of RBLs for port configuration.")
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# Two dummy rows plus replica even if we don't add the column
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self.extra_rows = sum(self.rbl)
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# Two dummy cols plus replica if we add the column
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self.extra_cols = len(self.left_rbl) + len(self.right_rbl)
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# If we aren't using row/col caps, then we need to use the bitcell
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if not self.cell.end_caps:
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self.extra_rows += 2
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self.extra_cols += 2
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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# We don't offset this because we need to align
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# the replica bitcell in the control logic
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# self.offset_all_coordinates()
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def create_netlist(self):
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""" Create and connect the netlist """
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self.add_modules()
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self.add_pins()
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self.create_instances()
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def add_modules(self):
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""" Array and dummy/replica columns
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d or D = dummy cell (caps to distinguish grouping)
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r or R = replica cell (caps to distinguish grouping)
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b or B = bitcell
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replica columns 1
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v v
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bdDDDDDDDDDDDDDDdb <- Dummy row
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bdDDDDDDDDDDDDDDrb <- Dummy row
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br--------------rb
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br| Array |rb
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br| row x col |rb
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br--------------rb
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brDDDDDDDDDDDDDDdb <- Dummy row
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bdDDDDDDDDDDDDDDdb <- Dummy row
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^^^^^^^^^^^^^^^
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dummy rows cols x 1
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^ dummy columns ^
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1 x (rows + 4)
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"""
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# Bitcell array
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self.bitcell_array = factory.create(module_type="bitcell_array",
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column_offset=1 + len(self.left_rbl),
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cols=self.column_size,
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rows=self.row_size)
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# Replica bitlines
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self.replica_columns = {}
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for port in self.all_ports:
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if port in self.left_rbl:
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# We will always have self.rbl[0] rows of replica wordlines below
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# the array.
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# These go from the top (where the bitcell array starts ) down
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replica_bit = self.rbl[0] - port
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column_offset = self.rbl[0]
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elif port in self.right_rbl:
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# We will always have self.rbl[0] rows of replica wordlines below
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# the array.
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# These go from the bottom up
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replica_bit = self.rbl[0] + self.row_size + port
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column_offset = self.rbl[0] + self.column_size + 1
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else:
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continue
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self.replica_columns[port] = factory.create(module_type="replica_column",
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rows=self.row_size,
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rbl=self.rbl,
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column_offset=column_offset,
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replica_bit=replica_bit)
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# Dummy row
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self.dummy_row = factory.create(module_type="dummy_array",
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cols=self.column_size,
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rows=1,
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# dummy column + left replica column
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column_offset=1 + len(self.left_rbl),
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mirror=0)
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# Dummy Row or Col Cap, depending on bitcell array properties
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col_cap_module_type = ("col_cap_array" if self.cell.end_caps else "dummy_array")
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self.col_cap_top = factory.create(module_type=col_cap_module_type,
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cols=self.column_size,
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rows=1,
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# dummy column + left replica column(s)
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column_offset=1 + len(self.left_rbl),
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mirror=0,
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location="top")
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self.col_cap_bottom = factory.create(module_type=col_cap_module_type,
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cols=self.column_size,
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rows=1,
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# dummy column + left replica column(s)
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column_offset=1 + len(self.left_rbl),
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mirror=0,
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location="bottom")
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# Dummy Col or Row Cap, depending on bitcell array properties
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row_cap_module_type = ("row_cap_array" if self.cell.end_caps else "dummy_array")
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self.row_cap_left = factory.create(module_type=row_cap_module_type,
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cols=1,
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column_offset=0,
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rows=self.row_size + self.extra_rows,
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mirror=(self.rbl[0] + 1) % 2)
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self.row_cap_right = factory.create(module_type=row_cap_module_type,
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cols=1,
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# dummy column
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# + left replica column(s)
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# + bitcell columns
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# + right replica column(s)
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column_offset=1 + len(self.left_rbl) + self.column_size + self.rbl[0],
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rows=self.row_size + self.extra_rows,
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mirror=(self.rbl[0] + 1) %2)
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def add_pins(self):
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# Arrays are always:
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# bitlines (column first then port order)
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# word lines (row first then port order)
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# dummy wordlines
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# replica wordlines
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# regular wordlines (bottom to top)
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# # dummy bitlines
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# replica bitlines (port order)
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# regular bitlines (left to right port order)
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#
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# vdd
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# gnd
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self.add_bitline_pins()
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self.add_wordline_pins()
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def add_bitline_pins(self):
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# The bit is which port the RBL is for
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for bit in self.rbls:
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for port in self.all_ports:
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self.rbl_bitline_names[bit].append("rbl_bl_{0}_{1}".format(port, bit))
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for port in self.all_ports:
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self.rbl_bitline_names[bit].append("rbl_br_{0}_{1}".format(port, bit))
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# Make a flat list too
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self.all_rbl_bitline_names = [x for sl in self.rbl_bitline_names for x in sl]
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self.bitline_names = self.bitcell_array.bitline_names
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# Make a flat list too
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self.all_bitline_names = [x for sl in zip(*self.bitline_names) for x in sl]
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for port in self.left_rbl:
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self.add_pin_list(self.rbl_bitline_names[port], "INOUT")
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self.add_pin_list(self.all_bitline_names, "INOUT")
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for port in self.right_rbl:
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self.add_pin_list(self.rbl_bitline_names[port], "INOUT")
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def add_wordline_pins(self):
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# Wordlines to ground
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self.gnd_wordline_names = []
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for port in self.all_ports:
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for bit in self.all_ports:
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self.rbl_wordline_names[port].append("rbl_wl_{0}_{1}".format(port, bit))
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if bit != port:
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self.gnd_wordline_names.append("rbl_wl_{0}_{1}".format(port, bit))
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self.all_rbl_wordline_names = [x for sl in self.rbl_wordline_names for x in sl]
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self.wordline_names = self.bitcell_array.wordline_names
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self.all_wordline_names = self.bitcell_array.all_wordline_names
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# All wordlines including dummy and RBL
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self.replica_array_wordline_names = []
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self.replica_array_wordline_names.extend(["gnd"] * len(self.col_cap_top.get_wordline_names()))
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for bit in range(self.rbl[0]):
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self.replica_array_wordline_names.extend([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[bit]])
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self.replica_array_wordline_names.extend(self.all_wordline_names)
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for bit in range(self.rbl[1]):
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self.replica_array_wordline_names.extend([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[self.rbl[0] + bit]])
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self.replica_array_wordline_names.extend(["gnd"] * len(self.col_cap_top.get_wordline_names()))
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for port in range(self.rbl[0]):
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self.add_pin(self.rbl_wordline_names[port][port], "INPUT")
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self.add_pin_list(self.all_wordline_names, "INPUT")
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for port in range(self.rbl[0], self.rbl[0] + self.rbl[1]):
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self.add_pin(self.rbl_wordline_names[port][port], "INPUT")
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def create_instances(self):
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""" Create the module instances used in this design """
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self.supplies = ["vdd", "gnd"]
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# Used for names/dimensions only
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self.cell = factory.create(module_type=OPTS.bitcell)
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# Main array
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self.bitcell_array_inst=self.add_inst(name="bitcell_array",
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mod=self.bitcell_array)
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self.connect_inst(self.all_bitline_names + self.all_wordline_names + self.supplies)
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# Replica columns
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self.replica_col_insts = []
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for port in self.all_ports:
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if port in self.rbls:
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self.replica_col_insts.append(self.add_inst(name="replica_col_{}".format(port),
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mod=self.replica_columns[port]))
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self.connect_inst(self.rbl_bitline_names[port] + self.replica_array_wordline_names + self.supplies)
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else:
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self.replica_col_insts.append(None)
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# Dummy rows under the bitcell array (connected with with the replica cell wl)
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self.dummy_row_replica_insts = []
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# Note, this is the number of left and right even if we aren't adding the columns to this bitcell array!
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for port in self.all_ports:
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self.dummy_row_replica_insts.append(self.add_inst(name="dummy_row_{}".format(port),
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mod=self.dummy_row))
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self.connect_inst(self.all_bitline_names + [x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[port]] + self.supplies)
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# Top/bottom dummy rows or col caps
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self.dummy_row_insts = []
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self.dummy_row_insts.append(self.add_inst(name="dummy_row_bot",
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mod=self.col_cap_bottom))
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self.connect_inst(self.all_bitline_names + ["gnd"] * len(self.col_cap_bottom.get_wordline_names()) + self.supplies)
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self.dummy_row_insts.append(self.add_inst(name="dummy_row_top",
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mod=self.col_cap_top))
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self.connect_inst(self.all_bitline_names + ["gnd"] * len(self.col_cap_top.get_wordline_names()) + self.supplies)
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# Left/right Dummy columns
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self.dummy_col_insts = []
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self.dummy_col_insts.append(self.add_inst(name="dummy_col_left",
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mod=self.row_cap_left))
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self.connect_inst(["dummy_left_" + bl for bl in self.row_cap_left.all_bitline_names] + self.replica_array_wordline_names + self.supplies)
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self.dummy_col_insts.append(self.add_inst(name="dummy_col_right",
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mod=self.row_cap_right))
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self.connect_inst(["dummy_right_" + bl for bl in self.row_cap_right.all_bitline_names] + self.replica_array_wordline_names + self.supplies)
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def create_layout(self):
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# This creates space for the unused wordline connections as well as the
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# row-based or column based power and ground lines.
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self.vertical_pitch = getattr(self, "{}_pitch".format(self.supply_stack[0]))
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self.horizontal_pitch = getattr(self, "{}_pitch".format(self.supply_stack[2]))
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self.unused_offset = vector(0.25, 0.25)
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# This is a bitcell x bitcell offset to scale
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self.bitcell_offset = vector(self.cell.width, self.cell.height)
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self.col_end_offset = vector(self.cell.width, self.cell.height)
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self.row_end_offset = vector(self.cell.width, self.cell.height)
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# Everything is computed with the main array
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self.bitcell_array_inst.place(offset=self.unused_offset)
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self.add_replica_columns()
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self.add_end_caps()
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# Array was at (0, 0) but move everything so it is at the lower left
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# We move DOWN the number of left RBL even if we didn't add the column to this bitcell array
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# Note that this doesn't include the row/col cap
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array_offset = self.bitcell_offset.scale(1 + len(self.left_rbl), 1 + self.rbl[0])
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self.translate_all(array_offset.scale(-1, -1))
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# Add extra width on the left and right for the unused WLs
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self.width = self.dummy_col_insts[1].rx() + self.unused_offset.x
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self.height = self.dummy_row_insts[1].uy()
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self.add_layout_pins()
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self.route_supplies()
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self.route_unused_wordlines()
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lower_left = self.find_lowest_coords()
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upper_right = self.find_highest_coords()
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self.width = upper_right.x - lower_left.x
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self.height = upper_right.y - lower_left.y
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self.translate_all(lower_left)
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self.add_boundary()
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self.DRC_LVS()
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def get_main_array_top(self):
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""" Return the top of the main bitcell array. """
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return self.bitcell_array_inst.uy()
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def get_main_array_bottom(self):
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""" Return the bottom of the main bitcell array. """
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return self.bitcell_array_inst.by()
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def get_main_array_left(self):
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""" Return the left of the main bitcell array. """
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return self.bitcell_array_inst.lx()
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def get_main_array_right(self):
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""" Return the right of the main bitcell array. """
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return self.bitcell_array_inst.rx()
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def get_replica_top(self):
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""" Return the top of all replica columns. """
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return self.dummy_row_insts[0].by()
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def get_replica_bottom(self):
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""" Return the bottom of all replica columns. """
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return self.dummy_row_insts[0].uy()
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def get_replica_left(self):
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""" Return the left of all replica columns. """
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return self.dummy_col_insts[0].rx()
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def get_replica_right(self):
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""" Return the right of all replica columns. """
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return self.dummy_col_insts[1].rx()
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def get_column_offsets(self):
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"""
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Return an array of the x offsets of all the regular bits
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"""
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offsets = [x + self.bitcell_array_inst.lx() for x in self.bitcell_array.get_column_offsets()]
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return offsets
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def add_replica_columns(self):
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""" Add replica columns on left and right of array """
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# Grow from left to right, toward the array
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for bit, port in enumerate(self.left_rbl):
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offset = self.bitcell_offset.scale(-len(self.left_rbl) + bit, -self.rbl[0] - 1) + self.unused_offset
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self.replica_col_insts[bit].place(offset)
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# Grow to the right of the bitcell array, array outward
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for bit, port in enumerate(self.right_rbl):
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offset = self.bitcell_array_inst.lr() + self.bitcell_offset.scale(bit, -self.rbl[0] - 1)
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self.replica_col_insts[self.rbl[0] + bit].place(offset)
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# Replica dummy rows
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# Add the dummy rows even if we aren't adding the replica column to this bitcell array
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# These grow up, toward the array
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for bit in range(self.rbl[0]):
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dummy_offset = self.bitcell_offset.scale(0, -self.rbl[0] + bit + (-self.rbl[0] + bit) % 2) + self.unused_offset
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self.dummy_row_replica_insts[bit].place(offset=dummy_offset,
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mirror="MX" if (-self.rbl[0] + bit) % 2 else "R0")
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# These grow up, away from the array
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for bit in range(self.rbl[1]):
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dummy_offset = self.bitcell_offset.scale(0, bit + bit % 2) + self.bitcell_array_inst.ul()
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self.dummy_row_replica_insts[self.rbl[0] + bit].place(offset=dummy_offset,
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mirror="MX" if (self.row_size + bit) % 2 else "R0")
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def add_end_caps(self):
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""" Add dummy cells or end caps around the array """
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# Far top dummy row (first row above array is NOT flipped if even number of rows)
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flip_dummy = (self.row_size + self.rbl[1]) % 2
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dummy_row_offset = self.bitcell_offset.scale(0, self.rbl[1] + flip_dummy) + self.bitcell_array_inst.ul()
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self.dummy_row_insts[1].place(offset=dummy_row_offset,
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mirror="MX" if flip_dummy else "R0")
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# Far bottom dummy row (first row below array IS flipped)
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flip_dummy = (self.rbl[0] + 1) % 2
|
|
dummy_row_offset = self.bitcell_offset.scale(0, -self.rbl[0] - 1 + flip_dummy) + self.unused_offset
|
|
self.dummy_row_insts[0].place(offset=dummy_row_offset,
|
|
mirror="MX" if flip_dummy else "R0")
|
|
# Far left dummy col
|
|
# Shifted down by the number of left RBLs even if we aren't adding replica column to this bitcell array
|
|
dummy_col_offset = self.bitcell_offset.scale(-len(self.left_rbl) - 1, -self.rbl[0] - 1) + self.unused_offset
|
|
self.dummy_col_insts[0].place(offset=dummy_col_offset)
|
|
|
|
# Far right dummy col
|
|
# Shifted down by the number of left RBLs even if we aren't adding replica column to this bitcell array
|
|
dummy_col_offset = self.bitcell_offset.scale(len(self.right_rbl), -self.rbl[0] - 1) + self.bitcell_array_inst.lr()
|
|
self.dummy_col_insts[1].place(offset=dummy_col_offset)
|
|
|
|
def add_layout_pins(self):
|
|
""" Add the layout pins """
|
|
|
|
# All wordlines
|
|
# Main array wl and bl/br
|
|
for pin_name in self.all_wordline_names:
|
|
pin_list = self.bitcell_array_inst.get_pins(pin_name)
|
|
for pin in pin_list:
|
|
self.add_layout_pin(text=pin_name,
|
|
layer=pin.layer,
|
|
offset=pin.ll().scale(0, 1),
|
|
width=self.width,
|
|
height=pin.height())
|
|
|
|
# Replica wordlines (go by the row instead of replica column because we may have to add a pin
|
|
# even though the column is in another local bitcell array)
|
|
for (names, inst) in zip(self.rbl_wordline_names, self.dummy_row_replica_insts):
|
|
for (wl_name, pin_name) in zip(names, self.dummy_row.get_wordline_names()):
|
|
if wl_name in self.gnd_wordline_names:
|
|
continue
|
|
pin = inst.get_pin(pin_name)
|
|
self.add_layout_pin(text=wl_name,
|
|
layer=pin.layer,
|
|
offset=pin.ll().scale(0, 1),
|
|
width=self.width,
|
|
height=pin.height())
|
|
|
|
for pin_name in self.all_bitline_names:
|
|
pin_list = self.bitcell_array_inst.get_pins(pin_name)
|
|
for pin in pin_list:
|
|
self.add_layout_pin(text=pin_name,
|
|
layer=pin.layer,
|
|
offset=pin.ll().scale(1, 0),
|
|
width=pin.width(),
|
|
height=self.height)
|
|
|
|
# Replica bitlines
|
|
if len(self.rbls) > 0:
|
|
for (names, inst) in zip(self.rbl_bitline_names, self.replica_col_insts):
|
|
pin_names = self.replica_columns[self.rbls[0]].all_bitline_names
|
|
for (bl_name, pin_name) in zip(names, pin_names):
|
|
pin = inst.get_pin(pin_name)
|
|
self.add_layout_pin(text=bl_name,
|
|
layer=pin.layer,
|
|
offset=pin.ll().scale(1, 0),
|
|
width=pin.width(),
|
|
height=self.height)
|
|
|
|
def route_supplies(self):
|
|
|
|
if OPTS.bitcell == "pbitcell":
|
|
bitcell = factory.create(module_type="pbitcell")
|
|
else:
|
|
bitcell = getattr(props, "bitcell_{}port".format(OPTS.num_ports))
|
|
|
|
wl_layer = bitcell.wl_layer
|
|
wl_dir = bitcell.wl_dir
|
|
|
|
bl_layer = bitcell.bl_layer
|
|
bl_dir = bitcell.bl_dir
|
|
|
|
vdd_layer = bitcell.vdd_layer
|
|
vdd_dir = bitcell.vdd_dir
|
|
|
|
gnd_layer = bitcell.gnd_layer
|
|
gnd_dir = bitcell.gnd_dir
|
|
|
|
# vdd/gnd are only connected in the perimeter cells
|
|
supply_insts = self.dummy_col_insts + self.dummy_row_insts
|
|
|
|
# For the wordlines
|
|
top_bot_mult = 1
|
|
left_right_mult = 1
|
|
|
|
vdd_locs = []
|
|
gnd_locs = []
|
|
# There are always vertical pins for the WLs on the left/right if we have unused wordlines
|
|
self.left_gnd_locs = self.route_side_pin("gnd", "left", left_right_mult)
|
|
self.right_gnd_locs = self.route_side_pin("gnd","right", left_right_mult)
|
|
# This needs to be big enough so that they aren't in the same supply routing grid
|
|
left_right_mult = 4
|
|
|
|
if gnd_dir == "V":
|
|
self.top_gnd_locs = self.route_side_pin("gnd", "top", top_bot_mult)
|
|
self.bot_gnd_locs = self.route_side_pin("gnd", "bot", top_bot_mult)
|
|
# This needs to be big enough so that they aren't in the same supply routing grid
|
|
top_bot_mult = 4
|
|
|
|
if vdd_dir == "V":
|
|
self.top_vdd_locs = self.route_side_pin("vdd", "top", top_bot_mult)
|
|
self.bot_vdd_locs = self.route_side_pin("vdd", "bot", top_bot_mult)
|
|
elif vdd_dir == "H":
|
|
self.left_vdd_locs = self.route_side_pin("vdd", "left", left_right_mult)
|
|
self.right_vdd_locs = self.route_side_pin("vdd", "right", left_right_mult)
|
|
else:
|
|
debug.error("Invalid vdd direction {}".format(vdd_dir), -1)
|
|
|
|
|
|
for inst in supply_insts:
|
|
for pin in inst.get_pins("vdd"):
|
|
if vdd_dir == "V":
|
|
self.connect_side_pin(pin, "top", self.top_vdd_locs[0].y)
|
|
self.connect_side_pin(pin, "bot", self.bot_vdd_locs[0].y)
|
|
elif vdd_dir == "H":
|
|
self.connect_side_pin(pin, "left", self.left_vdd_locs[0].x)
|
|
self.connect_side_pin(pin, "right", self.right_vdd_locs[0].x)
|
|
|
|
|
|
for inst in supply_insts:
|
|
for pin in inst.get_pins("gnd"):
|
|
if gnd_dir == "V":
|
|
self.connect_side_pin(pin, "top", self.top_gnd_locs[0].y)
|
|
self.connect_side_pin(pin, "bot", self.bot_gnd_locs[0].y)
|
|
elif gnd_dir == "H":
|
|
self.connect_side_pin(pin, "left", self.left_gnd_locs[0].x)
|
|
self.connect_side_pin(pin, "right", self.right_gnd_locs[0].x)
|
|
|
|
|
|
def route_unused_wordlines(self):
|
|
""" Connect the unused RBL and dummy wordlines to gnd """
|
|
# This grounds all the dummy row word lines
|
|
for inst in self.dummy_row_insts:
|
|
for wl_name in self.col_cap_top.get_wordline_names():
|
|
pin = inst.get_pin(wl_name)
|
|
self.connect_side_pin(pin, "left", self.left_gnd_locs[0].x)
|
|
self.connect_side_pin(pin, "right", self.right_gnd_locs[0].x)
|
|
|
|
# Ground the unused replica wordlines
|
|
for (names, inst) in zip(self.rbl_wordline_names, self.dummy_row_replica_insts):
|
|
for (wl_name, pin_name) in zip(names, self.dummy_row.get_wordline_names()):
|
|
if wl_name in self.gnd_wordline_names:
|
|
pin = inst.get_pin(pin_name)
|
|
self.connect_side_pin(pin, "left", self.left_gnd_locs[0].x)
|
|
self.connect_side_pin(pin, "right", self.right_gnd_locs[0].x)
|
|
|
|
def route_side_pin(self, name, side, offset_multiple=1):
|
|
"""
|
|
Routes a vertical or horizontal pin on the side of the bbox.
|
|
The multiple specifies how many track offsets to be away from the side assuming
|
|
(0,0) (self.width, self.height)
|
|
"""
|
|
if side in ["left", "right"]:
|
|
return self.route_vertical_side_pin(name, side, offset_multiple)
|
|
elif side in ["top", "bottom", "bot"]:
|
|
return self.route_horizontal_side_pin(name, side, offset_multiple)
|
|
else:
|
|
debug.error("Invalid side {}".format(side), -1)
|
|
|
|
def route_vertical_side_pin(self, name, side, offset_multiple=1):
|
|
"""
|
|
Routes a vertical pin on the side of the bbox.
|
|
"""
|
|
if side == "left":
|
|
bot_loc = vector(-offset_multiple * self.vertical_pitch, 0)
|
|
top_loc = vector(-offset_multiple * self.vertical_pitch, self.height)
|
|
elif side == "right":
|
|
bot_loc = vector(self.width + offset_multiple * self.vertical_pitch, 0)
|
|
top_loc = vector(self.width + offset_multiple * self.vertical_pitch, self.height)
|
|
|
|
layer = self.supply_stack[2]
|
|
top_via = contact(layer_stack=self.supply_stack,
|
|
directions=("H", "H"))
|
|
|
|
|
|
# self.add_layout_pin_rect_ends(text=name,
|
|
# layer=layer,
|
|
# start=bot_loc,
|
|
# end=top_loc)
|
|
self.add_layout_pin_segment_center(text=name,
|
|
layer=layer,
|
|
start=bot_loc,
|
|
end=top_loc,
|
|
width=top_via.second_layer_width)
|
|
|
|
return (bot_loc, top_loc)
|
|
|
|
def route_horizontal_side_pin(self, name, side, offset_multiple=1):
|
|
"""
|
|
Routes a horizontal pin on the side of the bbox.
|
|
"""
|
|
if side in ["bottom", "bot"]:
|
|
left_loc = vector(0, -offset_multiple * self.horizontal_pitch)
|
|
right_loc = vector(self.width, -offset_multiple * self.horizontal_pitch)
|
|
elif side == "top":
|
|
left_loc = vector(0, self.height + offset_multiple * self.horizontal_pitch)
|
|
right_loc = vector(self.width, self.height + offset_multiple * self.horizontal_pitch)
|
|
|
|
layer = self.supply_stack[0]
|
|
side_via = contact(layer_stack=self.supply_stack,
|
|
directions=("V", "V"))
|
|
|
|
# self.add_layout_pin_rect_ends(text=name,
|
|
# layer=layer,
|
|
# start=left_loc,
|
|
# end=right_loc)
|
|
self.add_layout_pin_segment_center(text=name,
|
|
layer=layer,
|
|
start=left_loc,
|
|
end=right_loc,
|
|
width=side_via.first_layer_height)
|
|
|
|
return (left_loc, right_loc)
|
|
|
|
def connect_side_pin(self, pin, side, offset):
|
|
"""
|
|
Used to connect horizontal layers of pins to the left/right straps
|
|
locs provides the offsets of the pin strip end points.
|
|
"""
|
|
if side in ["left", "right"]:
|
|
self.connect_vertical_side_pin(pin, side, offset)
|
|
elif side in ["top", "bottom", "bot"]:
|
|
self.connect_horizontal_side_pin(pin, side, offset)
|
|
else:
|
|
debug.error("Invalid side {}".format(side), -1)
|
|
|
|
def connect_horizontal_side_pin(self, pin, side, yoffset):
|
|
"""
|
|
Used to connect vertical layers of pins to the top/bottom horizontal straps
|
|
"""
|
|
cell_loc = pin.center()
|
|
pin_loc = vector(cell_loc.x, yoffset)
|
|
|
|
# Place the pins a track outside of the array
|
|
self.add_via_stack_center(offset=pin_loc,
|
|
from_layer=pin.layer,
|
|
to_layer=self.supply_stack[0],
|
|
directions=("V", "V"))
|
|
|
|
# Add a path to connect to the array
|
|
self.add_path(pin.layer, [cell_loc, pin_loc])
|
|
|
|
|
|
def connect_vertical_side_pin(self, pin, side, xoffset):
|
|
"""
|
|
Used to connect vertical layers of pins to the top/bottom vertical straps
|
|
"""
|
|
cell_loc = pin.center()
|
|
pin_loc = vector(xoffset, cell_loc.y)
|
|
|
|
# Place the pins a track outside of the array
|
|
self.add_via_stack_center(offset=pin_loc,
|
|
from_layer=pin.layer,
|
|
to_layer=self.supply_stack[2],
|
|
directions=("H", "H"))
|
|
|
|
# Add a path to connect to the array
|
|
self.add_path(pin.layer, [cell_loc, pin_loc])
|
|
|
|
def analytical_power(self, corner, load):
|
|
"""Power of Bitcell array and bitline in nW."""
|
|
# Dynamic Power from Bitline
|
|
bl_wire = self.gen_bl_wire()
|
|
cell_load = 2 * bl_wire.return_input_cap()
|
|
bl_swing = OPTS.rbl_delay_percentage
|
|
freq = spice["default_event_frequency"]
|
|
bitline_dynamic = self.calc_dynamic_power(corner, cell_load, freq, swing=bl_swing)
|
|
|
|
# Calculate the bitcell power which currently only includes leakage
|
|
cell_power = self.cell.analytical_power(corner, load)
|
|
|
|
# Leakage power grows with entire array and bitlines.
|
|
total_power = self.return_power(cell_power.dynamic + bitline_dynamic * self.column_size,
|
|
cell_power.leakage * self.column_size * self.row_size)
|
|
return total_power
|
|
|
|
|
|
def gen_bl_wire(self):
|
|
if OPTS.netlist_only:
|
|
height = 0
|
|
else:
|
|
height = self.height
|
|
bl_pos = 0
|
|
bl_wire = self.generate_rc_net(int(self.row_size - bl_pos), height, drc("minwidth_m1"))
|
|
bl_wire.wire_c =spice["min_tx_drain_c"] + bl_wire.wire_c # 1 access tx d/s per cell
|
|
return bl_wire
|
|
|
|
def graph_exclude_bits(self, targ_row=None, targ_col=None):
|
|
"""
|
|
Excludes bits in column from being added to graph except target
|
|
"""
|
|
self.bitcell_array.graph_exclude_bits(targ_row, targ_col)
|
|
|
|
def graph_exclude_replica_col_bits(self):
|
|
"""
|
|
Exclude all replica/dummy cells in the replica columns except the replica bit.
|
|
"""
|
|
|
|
for port in self.left_rbl + self.right_rbl:
|
|
self.replica_columns[port].exclude_all_but_replica()
|
|
|
|
def get_cell_name(self, inst_name, row, col):
|
|
"""
|
|
Gets the spice name of the target bitcell.
|
|
"""
|
|
return self.bitcell_array.get_cell_name(inst_name + "{}x".format(OPTS.hier_seperator) + self.bitcell_array_inst.name, row, col)
|
|
|
|
def clear_exclude_bits(self):
|
|
"""
|
|
Clears the bit exclusions
|
|
"""
|
|
self.bitcell_array.init_graph_params()
|