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OpenRAM
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  • d7c3bbea3e crba passing again norbl/leftrbl Jesse Cirimelli-Low 2023-10-28 18:05:07 -0700
  • aa2cf88870
         Fix tabs/spaces in globals.py Mik Igor 2023-10-27 01:35:04 +0200
  • 173e47ae45
         Validate tech_name in config file iterating over technology dir Mik Igor 2023-10-27 01:29:27 +0200
  • 5811c5ce99
         FIX: scn3me_subm typo Mik Igor 2023-10-27 00:49:31 +0200
  • 189824429c
         Add freepdk45 to debug error in tech_name validation Mik Igor 2023-10-27 00:45:32 +0200
  • 123e43e942
         Add freepdk45 to tech_name validation in compiler/globals.py Mik Igor 2023-10-27 00:40:55 +0200
  • ce2b11ebd9
         Validate tech_name param in compiler/globals.py Mik Igor 2023-10-26 23:53:03 +0200
  • 3113798b13 Bump version: 1.2.39 -> 1.2.40 v1.2.40 vlsida-bot 2023-10-06 02:12:26 +0000
  • fe379297be Add timestamps to the log file Eren Dogan 2023-10-05 14:55:05 -0700
  • 6a6ac026db Bump version: 1.2.38 -> 1.2.39 v1.2.39 vlsida-bot 2023-09-28 19:50:40 +0000
  • a5412902c6 all control logic tests pass now Sam Crow 2023-09-27 16:25:02 -0700
  • 1b13d4369e Bump version: 1.2.37 -> 1.2.38 v1.2.38 vlsida-bot 2023-09-27 23:25:24 +0000
  • bf49ea744e force multi-delay chain pinouts to be user configurable Sam Crow 2023-09-27 13:15:45 -0700
  • c47ec37473 Bump version: 1.2.36 -> 1.2.37 v1.2.37 vlsida-bot 2023-09-26 20:04:03 +0000
  • 0a3889a2a6 Revert "use new magic version with drc catchup fix" Sam Crow 2023-09-26 11:37:34 -0700
  • 5b282df667 Revert "add drc style drc(full) to run_drc.sh on Tim Edwards recommondation" Sam Crow 2023-09-26 11:37:04 -0700
  • c4a14b9354 add drc style drc(full) to run_drc.sh on Tim Edwards recommondation Sam Crow 2023-09-25 14:14:27 -0700
  • ad2468cc26 use new magic version with drc catchup fix Sam Crow 2023-09-25 14:08:38 -0700
  • 2e55385cd6 Bump version: 1.2.35 -> 1.2.36 v1.2.36 vlsida-bot 2023-09-20 23:25:59 +0000
  • 3b6cc2f3a8 Hardcode tool versions in install_conda.sh Eren Dogan 2023-09-20 14:58:58 -0700
  • 2faa067ea6 add support for col offset to rbc; fix rba mirroring Jesse Cirimelli-Low 2023-09-12 12:12:21 -0700
  • 0034798787 both rbl replica array working Jesse Cirimelli-Low 2023-09-11 11:23:39 -0700
  • 1a8c27c549 Bump version: 1.2.34 -> 1.2.35 v1.2.35 vlsida-bot 2023-09-09 22:09:16 +0000
  • b3e1a163d0 Fix derouting wires in the gridless router Eren Dogan 2023-09-09 13:32:16 -0700
  • e553f3db41 fix sram.sp spare_wen Jesse Cirimelli-Low 2023-09-07 12:24:39 -0700
  • 9c66473cc9 Bump version: 1.2.33 -> 1.2.34 v1.2.34 vlsida-bot 2023-09-07 06:07:59 +0000
  • 995cc4f60f Fix typo Eren Dogan 2023-09-06 21:38:19 -0700
  • 099869d4c9 Fix typos Eren Dogan 2023-09-03 18:35:07 -0700
  • 3f2d61a0fa Prevent same file error when copying the config file (VLSIDA/PrivateRAM#108) Eren Dogan 2023-09-03 18:21:31 -0700
  • eb82053ab8 copy router from dev Jesse Cirimelli-Low 2023-09-03 13:16:18 -0700
  • 5605154cc2 merge dev Jesse Cirimelli-Low 2023-09-02 12:27:38 -0700
  • 1a25fcf9a5 Bump version: 1.2.32 -> 1.2.33 v1.2.33 vlsida-bot 2023-09-02 18:43:35 +0000
  • abb12bd785 Increase non-preferred direction cost in router Eren Dogan 2023-09-02 08:00:58 -0700
  • 775922774a Use bbox trees to iterate over shapes in routing region efficiently Eren Dogan 2023-09-01 20:37:07 -0700
  • 066d00f44b increase power ring crba width for drc Jesse Cirimelli-Low 2023-09-01 02:02:41 -0700
  • d9004f6de6 Print more info for the routing processes Eren Dogan 2023-08-31 19:03:31 -0700
  • 8a60684e51 Increase the routing region inflation to be safer Eren Dogan 2023-08-31 18:26:45 -0700
  • a9e63efad7 Increase via cost in router Eren Dogan 2023-08-31 18:26:04 -0700
  • c9a848550c Revert "merge dev" Jesse Cirimelli-Low 2023-08-30 22:40:35 -0700
  • daec840888 merge dev Jesse Cirimelli-Low 2023-08-30 22:04:42 -0700
  • 29e80e8f25 bump sky130 sram library Jesse Cirimelli-Low 2023-08-30 21:18:50 -0700
  • 0cba6a6050 single port sky130 crba passing lvs Jesse Cirimelli-Low 2023-08-30 20:59:02 -0700
  • b281771753 Bump version: 1.2.31 -> 1.2.32 v1.2.32 vlsida-bot 2023-08-30 16:52:07 +0000
  • 56bee27ee3 Don't write/read gds files unnecessarily for router Eren Dogan 2023-08-29 21:45:52 -0700
  • 8f2e4c6914 power ring working Jesse Cirimelli-Low 2023-08-28 22:15:05 -0700
  • b525ba60a0 Bump version: 1.2.30 -> 1.2.31 v1.2.31 vlsida-bot 2023-08-28 21:12:21 +0000
  • 8794070ebc various refactor changes Jesse Cirimelli-Low 2023-08-28 12:31:55 -0700
  • e12ab68362 Simplify closest edge calculation in signal escape router Eren Dogan 2023-08-28 10:38:53 -0700
  • fa5de05be3 Merge branch 'dev' into gridless_router Eren Dogan 2023-08-27 21:17:58 -0700
  • 53cc99f5c1 Perform signal escape routing in smaller regions Eren Dogan 2023-08-27 21:16:34 -0700
  • 9df3c2ac59 Return the path in source-to-target order Eren Dogan 2023-08-27 21:15:25 -0700
  • 141a4e3380 Don't scale the routing region if no path is found Eren Dogan 2023-08-27 15:42:09 -0700
  • ba51149dce placement working for sp capped rba, need fix rowcap patterns Jesse Cirimelli-Low 2023-08-26 18:54:07 -0700
  • 0ac2922573 Bump version: 1.2.29 -> 1.2.30 v1.2.30 vlsida-bot 2023-08-26 22:17:23 +0000
  • ca5ca0c7a8 bump sram library commit to fix colenda gds Jesse Cirimelli-Low 2023-08-26 15:29:08 -0500
  • 72a7b0342b work on capped rba Jesse Cirimelli-Low 2023-08-25 16:39:32 -0700
  • 036cc54b99 rba done w/o wordline Jesse Cirimelli-Low 2023-08-24 02:55:45 -0700
  • 64b0cd25d7 replica col passing Jesse Cirimelli-Low 2023-08-22 01:16:35 -0700
  • a05ab6e908 route supplies + fix replica col dummy Jesse Cirimelli-Low 2023-08-22 01:09:19 -0700
  • 450f8ab0c3 replica col generating, funny dummy cell placement Jesse Cirimelli-Low 2023-08-22 00:45:57 -0700
  • 5cf50b333a bitcell array passing Jesse Cirimelli-Low 2023-08-21 20:25:51 -0700
  • f890160601 add nwell routing in bca Jesse Cirimelli-Low 2023-08-21 20:12:36 -0700
  • 5a6c78865d singleport bitcell array laying out Jesse Cirimelli-Low 2023-08-21 19:24:06 -0700
  • 9ac894e2ef update bitcell array trimming Jesse Cirimelli-Low 2023-08-15 11:30:16 -0700
  • bb47452baf reapply commit c8a06a1 patch that was incorrectly reverted Sam Crow 2023-08-15 11:07:04 -0700
  • e4c15d33c4 Merge branch 'singleport_refactor' of github.com:VLSIDA/PrivateRAM into singleport_refactor Jesse Cirimelli-Low 2023-08-14 18:53:22 -0700
  • cd1b0f973d Revert pin/net spice object work Sam Crow 2023-08-14 18:30:40 -0700
  • 0391bf6593 add dummy mirroring for sky130 dp Jesse Cirimelli-Low 2023-08-14 14:25:57 -0700
  • 30ee5a0a2e add dummy cell mirroring for sky130 Jesse Cirimelli-Low 2023-08-14 14:19:58 -0700
  • 74c12f944f mirror skywater dp Jesse Cirimelli-Low 2023-08-14 13:59:31 -0700
  • fde1b056dc Merge branch 'dev' into singleport_refactor Jesse Cirimelli-Low 2023-08-11 13:45:42 -0700
  • 0111620c91 deepcopy overide for instance Jesse Cirimelli-Low 2023-08-11 13:45:24 -0700
  • 3eaf973d89 Bump version: 1.2.28 -> 1.2.29 v1.2.29 vlsida-bot 2023-08-11 02:14:32 +0000
  • e23289d5ae merge in dev Jesse Cirimelli-Low 2023-08-10 17:04:45 -0700
  • 230454d567 Merge changes from subprocess_fix Bugra Onal 2023-08-10 16:19:28 -0700
  • 3f08c848d7 Force to use bash for simulators Bugra Onal 2023-08-10 16:05:24 -0700
  • be72bcfa01 trim bitcells and fix replica column excluding Jesse Cirimelli-Low 2023-08-10 00:34:16 -0700
  • 3fc2a1e229 remove print statements Jesse Cirimelli-Low 2023-08-09 22:59:43 -0700
  • cc8161afc1 Bump version: 1.2.27 -> 1.2.28 v1.2.28 vlsida-bot 2023-08-10 05:09:47 +0000
  • ea02aae40f Find blocked nodes and probes faster Eren Dogan 2023-08-09 17:45:49 -0700
  • 6f4ee4ad2d pass modules by pointer not value Jesse Cirimelli-Low 2023-08-09 14:06:35 -0700
  • 9ac82060b9 Simplify 'remove' attribute of graph_node Eren Dogan 2023-08-08 11:54:12 -0700
  • ad05fde099 Bump version: 1.2.26 -> 1.2.27 v1.2.27 vlsida-bot 2023-08-04 01:45:27 +0000
  • 1aa04db2b6 add isntance naming templates Jesse Cirimelli-Low 2023-08-03 16:24:24 -0700
  • 5e01bad2ee remove whitespace Jesse Cirimelli-Low 2023-08-03 00:42:42 -0700
  • fa1b2fc96e Delete unused file Eren Dogan 2023-08-02 21:54:45 -0700
  • f8b2c1e9b9 Change OPTS.route_supplies option since there's only one router now Eren Dogan 2023-08-02 21:48:29 -0700
  • 8fff4e2635 Organize imports of the new router Eren Dogan 2023-08-02 21:35:13 -0700
  • 54fc34392d Remove unnecessary imports Eren Dogan 2023-08-02 21:28:21 -0700
  • e1d0902680 Cleanup the new router Eren Dogan 2023-08-02 21:26:24 -0700
  • ba8e80d205 Replace layout pins in the new signal escape router Eren Dogan 2023-08-02 19:33:48 -0700
  • 87eca6b7db Use the initial bbox to route supply and signals Eren Dogan 2023-08-02 18:01:09 -0700
  • 08dad81214 Use the same inflating rules for all shapes in router Eren Dogan 2023-08-02 17:48:56 -0700
  • 61cfa55d75 fix replica col Jesse Cirimelli-Low 2023-08-02 15:19:48 -0700
  • 5b0f97860a Calculate bbox inside the router Eren Dogan 2023-08-02 09:30:50 -0700
  • 937585d23c Route signals to the perimeter in sorted order Eren Dogan 2023-08-01 21:17:43 -0700
  • 877f20e071 Use the new routers in ROMs Eren Dogan 2023-08-01 19:10:02 -0700
  • 5a764c9d43 remove MY mirroring in scmos Jesse Cirimelli-Low 2023-08-01 19:05:55 -0700
  • 887a66553b Implement signal escape router using the new gridless router Eren Dogan 2023-08-01 12:46:02 -0700
  • dd152da5c2 Change signal escape router's high-level function name Eren Dogan 2023-08-01 11:26:25 -0700