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OpenRAM
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2732 Commits

Author SHA1 Message Date
mrg 8ce23d7f17 Provide unique WL driver instance name 2020-10-01 07:17:32 -07:00
mrg bd125e2ed3 Check for duplicate instance names. 2020-10-01 07:17:16 -07:00
Matt Guthaus 2b475670f7 Check for failed result in functional simulation 2020-09-30 12:40:07 -07:00
Matt Guthaus 112d57d90a Enable riscv tests 2020-09-30 12:39:40 -07:00
mrg f4e6a8895b Update riscv unit test 2020-09-30 08:50:58 -07:00
jcirimel 7cbf456a4f sky130 rba done 2020-09-30 07:34:05 -07:00
mrg b147e8485c PEP8 formatting 2020-09-29 16:52:27 -07:00
mrg 066570bfeb Fix length of write driver 2020-09-29 16:51:55 -07:00
mrg 8e908f016e PEP8 formatting 2020-09-29 13:43:59 -07:00
mrg bca69b24e3 Optional number of functional cycles 2020-09-29 13:43:54 -07:00
mrg 54890a8d77 Add new golden data 2020-09-29 13:43:34 -07:00
mrg 449a4c2660 Exclude bitcells in other local areas not of interest 2020-09-29 12:15:42 -07:00
mrg 0c280e062a Fix func test with row/col of 0. PEP8 cleanup. Smaller global test case. 2020-09-29 11:35:58 -07:00
mrg 4b5bbe755f PEP8 cleanup. Fix cur_slew bug. 2020-09-29 11:13:58 -07:00
mrg 9032bb9869 Add global wordline delay test 2020-09-29 10:28:57 -07:00
mrg d7e2340e62 Lots of PEP8 cleanup. Refactor path graph to simulation class. 2020-09-29 10:26:31 -07:00
mrg 1eb8798bb6 Add global functional test 2020-09-28 16:12:09 -07:00
mrg b2dab486fc Add draft of path exclusion calls 2020-09-28 16:05:21 -07:00
mrg 4a987bef9a Merge branch 'wlbuffer' into dev 2020-09-28 15:51:45 -07:00
mrg 159c04a25d Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2020-09-28 15:51:35 -07:00
mrg 70c90ca7fb Replica bitcell array bbox to include unused WL gnd pins. 2020-09-28 14:49:33 -07:00
mrg 9c6d8d7aed Zjob to bottom. 2020-09-28 13:16:03 -07:00
mrg 5ab0d01779 Remove zjog and go with L shape. 2020-09-28 12:48:37 -07:00
mrg d65eb16513 Zjog the WL enable. Min driver is 1. 2020-09-28 12:24:55 -07:00
mrg 6f06bb9dd5 Create sized RBL WL driver in port_address 2020-09-28 11:30:21 -07:00
mrg 88731ccd8e Fix rounding error for wmask with various word_size 2020-09-28 09:53:01 -07:00
jcirimel 3dd72cdeac progress with rba pin mismatch 2020-09-23 08:37:32 -07:00
jcirimel 17e6e5eb16 row end col done 2020-09-23 08:02:56 -07:00
jcirimel 5c263e0001 rep col done w/o power pins 2020-09-23 06:24:52 -07:00
jcirimel 7afe3ea52c replica col arrangement done 2020-09-23 04:51:09 -07:00
jcirimel 7f8edf6d7c fix replica bitcell col 2020-09-23 00:36:08 -07:00
jcirimel efdc171b14 make split wl specific to each port 2020-09-23 00:08:34 -07:00
jcirimel fb6a665514 removed references to technology name 2020-09-22 18:33:03 -07:00
jcirimel de33ab3761 fix single port bitcell pattern 2020-09-22 15:08:53 -07:00
mrg c7d32089f3 Create RBL wordline buffer with correct polarity. 2020-09-17 14:45:49 -07:00
jcirimel 559dfbc7a6 single port bitcell array done 2020-09-16 05:46:14 -07:00
mrg 392afd4d4b Add unit test for hierarchical wordline. 2020-09-15 13:46:21 -07:00
mrg 11f2b6b809 Do not do final verification if supplies were not routed 2020-09-15 13:39:00 -07:00
mrg e7ad22ff69 Separate WL via from bitell array to avoid grounded WLs 2020-09-15 13:38:28 -07:00
mrg 5e94d76127 Make global bitline only as wide as needed rather than whole array 2020-09-15 13:24:38 -07:00
mrg aff3cd2aab Update length of control bus 2020-09-15 09:49:00 -07:00
jcirimel d22164bd48 single port progess 2020-09-14 18:11:38 -07:00
mrg f25b6ffa61 Make control bus height of port data 2020-09-14 15:42:17 -07:00
mrg 7b24d1f012 Use pins for write_driver dimensions 2020-09-14 14:42:28 -07:00
mrg 55dd4d0c47 Global bitcell array working 2020-09-14 14:35:52 -07:00
mrg deaaec1ede Fix width of write enable with spare columns 2020-09-14 13:09:45 -07:00
mrg c12720a93f Extend pin correct length in new array. 2020-09-14 12:53:59 -07:00
mrg e95ab66916 Update to space according to the bitcell array. 2020-09-14 12:05:45 -07:00
mrg 4482c63d6f Fix sense amp offset index error 2020-09-11 17:12:29 -07:00
mrg 8909ad7165 Update modules to use variable bit offsets. 
Bitcell arrays can return the bit offsets.
Port data and submodules can use offsets for spacing.
Default spacing for port data if no offsets given.
 2020-09-11 15:36:22 -07:00
mrg c58741c44f Updates to global array. 
Standardize bitcell array main array offsets.
Duplicate replica interface pins in global interface pins.
 2020-09-10 16:44:54 -07:00
mrg 9c762634a5 Change default options for replica_bitcell_array 2020-09-10 15:11:48 -07:00
mrg 71d86f88b0 Merge branch 'dev' into wlbuffer 2020-09-10 13:05:14 -07:00
mrg f2313d0c73 Use default names for replica_column too 2020-09-10 12:04:46 -07:00
mrg 3c0707e5d1 Consistents of bl x port then br x port 2020-09-09 13:38:13 -07:00
mrg 3062aba214 Fix update to exclude bits with RBLs 2020-09-09 13:03:05 -07:00
mrg 12fd60e8c3 Fix pbitcell array test 2020-09-09 12:02:09 -07:00
mrg 7bb21fb73f Updates to local and global arrays to make bitline and wordlines consistent. 2020-09-09 11:54:46 -07:00
Hunter Nichols af22e438f1 Added option to output an extended configuration file that includes defaults. 2020-09-08 18:40:39 -07:00
mrg 8e91ec1770 Add check_pins function 2020-09-08 13:31:50 -07:00
mrg 1269bf6e16 Global bitcell working 2020-09-04 13:06:58 -07:00
Hunter Nichols 8bcbf005bf Merge branch 'dev' into characterizer_bug_fixes 2020-09-04 02:25:01 -07:00
Hunter Nichols 500327d59b Fixed import in simulation and fixed names in functional 2020-09-04 02:24:18 -07:00
mrg 1534295326 Ground dummy lines in replica bitcell array 2020-09-03 14:04:20 -07:00
mrg f6f6242d68 Ground dummy lines in replica bitcell array 2020-09-03 10:45:28 -07:00
Hunter Nichols d027632bdc Moved majority of code duplicated between delay and functional to simulation 2020-09-02 14:22:18 -07:00
jcirimel 73443c8c95 Merge branch 'dev' into s8_single_port 2020-09-01 15:37:10 -07:00
mrg 4ec47d8ee1 Refactor global and local to be a bitcell_base_array 2020-09-01 11:59:01 -07:00
mrg c1c631abe1 Global bitcell array passes LVS/DRC 2020-09-01 10:57:49 -07:00
mrg 7bdce3ca9a Don't make dummy bitlines pins for simplicity 2020-09-01 09:55:23 -07:00
Hunter Nichols 13b1d4613c Moved spice naming checking code from design to the spice base module 2020-08-31 14:36:13 -07:00
Hunter Nichols 73b2277daa Removed dead code related to older characterization scheme 2020-08-27 17:30:58 -07:00
mrg c1c1535210 Merge branch 'wlbuffer' into dev 2020-08-27 15:44:29 -07:00
Hunter Nichols 42f2ff679e Removed dead code from delay and base module related to characterization 2020-08-27 15:40:41 -07:00
mrg 11a82b7283 Fixed local bitcell array for single and dual port 2020-08-27 14:03:05 -07:00
mrg da827d923f Merge branch 'wlbuffer' into dev 2020-08-26 10:00:34 -07:00
mrg c321d85595 Fix syntax error for dual port 2020-08-26 09:54:41 -07:00
mrg e92337ddaf Separate get_ and get_all for bitlines and wordlines 2020-08-25 17:08:48 -07:00
mrg 652f160aca Merge branch 'wlbuffer' into dev 2020-08-25 15:50:08 -07:00
mrg bdb18b4cab Fix disconnected replica pins 2020-08-25 14:51:49 -07:00
mrg bd8bf9afd8 Remove RBL label at top level of SRAM 2020-08-25 14:42:21 -07:00
mrg 856cce1e62 Add -json for detailed LVS output 2020-08-25 13:58:28 -07:00
mrg 28bd93bf51 Still working on array refactor 2020-08-25 11:50:44 -07:00
jcirimel 3f45d10797 fix column decoder 2020-08-25 02:46:16 -07:00
mrg 8dee5520e0 Standardize array names independent of bitcell 2020-08-21 13:44:35 -07:00
jcirimel 854d51c721 merge dev 2020-08-19 14:25:41 -07:00
mrg b762580ee2 Skip global test for now 2020-08-19 11:36:21 -07:00
mrg 593a98e29a Update local bitcell array for dual port 2020-08-19 11:35:55 -07:00
jcirimel b7ef5496c4 decoder drc clean 2020-08-19 00:39:55 -07:00
mrg e215c0e016 Drafting global bitcell array 2020-08-18 16:30:55 -07:00
mrg 5776788574 Order of wordlines and bitlines in bank 2020-08-18 16:30:38 -07:00
mrg 224e359208 Fix pin order for replica array 2020-08-18 15:59:05 -07:00
mrg f58fc6579f Rename local/global tests 2020-08-18 15:58:44 -07:00
mrg e3e4bac922 Fix replica bitcell array for right only RBL 2020-08-18 15:47:52 -07:00
mrg 59d65c46c3 Fix bug in not adding RBLs in local bitcell array 2020-08-18 15:11:10 -07:00
mrg 2643a96f97 Order inputs wordline, bitline, supply 2020-08-18 14:29:36 -07:00
mrg b288bba43e Add global bitcell array test 2020-08-18 14:29:23 -07:00
mrg f98fbb175b Merge branch 'wlbuffer' into dev 2020-08-18 10:06:52 -07:00
mrg e37a9234cc Update replica column call to new refactor 2020-08-18 09:14:50 -07:00
mrg 17504a7da3 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2020-08-18 09:01:41 -07:00
mrg bc974ff78e Update replica column unit tests for new refactor 2020-08-18 08:56:24 -07:00
jcirimel 9cecf367ee Merge branch 'dev' into pex 2020-08-17 17:49:41 -07:00
jcirimel 714b57d48e Merge branch 'dev' into pex 2020-08-17 17:48:21 -07:00
mrg 99e252d6d4 Update interface of RBL array 2020-08-17 17:19:07 -07:00
mrg b1e55f9072 Add local bitcell array 2020-08-17 15:14:42 -07:00
mrg 3a692e2846 Comment updates 2020-08-17 14:35:39 -07:00
mrg 60224b105f Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2020-08-17 14:20:34 -07:00
mrg 94bfad4113 Horizontal gnd vias for unused array inputs 2020-08-17 13:24:34 -07:00
mrg bddb251a84 More room for power contacts 2020-08-17 12:32:44 -07:00
mrg 2c43d315db Revert gds readonly true 2020-08-17 12:19:23 -07:00
mrg 35a1b00aa0 Extra space for unused wl contacts 2020-08-14 14:23:40 -07:00
mrg 170e3feb7d Fix order of replica wordlines and bitlines 2020-08-14 14:14:49 -07:00
mrg 604e433e22 Add readonly true for Magic scripts 2020-08-14 10:40:31 -07:00
mrg 2ac04efe2e Must connect for replica cells other than top/bottom 2020-08-13 16:26:19 -07:00
jcirimel e7c9914d77 decoder passing except for bus route 2020-08-13 16:20:39 -07:00
mrg 797c41c750 Skip local bitcell array test 2020-08-13 14:36:39 -07:00
mrg 50525e70f4 Fix up to SRAM level with new replica bitcell array ports. 2020-08-13 14:29:10 -07:00
mrg 8dbaa66aa5 Merge branch 'super' into dev 2020-08-12 14:25:13 -07:00
mrg 7ac4574e4f Use micron units for all simulation in sky130 2020-08-12 13:54:55 -07:00
mrg 5fc6438553 Fix pinv_dec super call 2020-08-12 13:22:28 -07:00
mrg 15c8c200f3 Undo super() in measurement abstract class 2020-08-12 12:10:12 -07:00
mrg 55814a8f74 Fix syntax errors in pgates for super edits 2020-08-12 11:15:32 -07:00
mrg 0bec6f0439 Fix SRAM to use simulation spice instead of LVS spice 2020-08-12 10:41:21 -07:00
mrg a55909930f Replace replcia_bitcell_array with new one in bank 2020-08-12 09:49:14 -07:00
mrg 8e890c2014 Replica bitcell with all the fixings 2020-08-11 15:00:29 -07:00
mrg 30976df48f Change inheritance inits to use super 2020-08-06 11:33:26 -07:00
mrg eef97ff215 Reabstracting bit and word line names. 2020-08-06 11:17:49 -07:00
mrg 037de96989 Merge branch 'dev' into wlbuffer 2020-08-05 10:37:29 -07:00
mrg 528cb07635 Merge branch 'dev' into wlbuffer 2020-08-05 10:01:43 -07:00
jcirimel 38648027d0 fix pinv unit test 2020-08-04 04:40:20 -07:00
jcirimel 02e65a00ef update pex to work with dev changes 2020-08-03 17:14:34 -07:00
Bob Vanhoof 9b8ef5ef57 fix: generated pex file was not passed correctly to lib characterizer 2020-08-03 10:16:12 +02:00
Bob Vanhoof 487bb6c6e9 Merge branch 'dev' of github:VLSIDA/OpenRAM into CalibrePexFilesUpdate 2020-08-03 09:32:27 +02:00
jcirimel 3221b4ec57 update to new metal stack names 2020-07-31 05:27:19 -07:00
Bob Vanhoof dc55ededc1 fix regession tests after calibre fix 2020-07-31 12:51:34 +02:00
mrg 487027a9f2 Fix pex file names 2020-07-30 11:35:13 -07:00
mrg 8fa0065aaf Undo PR 82 changes -- broke unit test. 2020-07-30 11:09:19 -07:00
mrg a663d903c5 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2020-07-30 08:44:25 -07:00
Matt Guthaus 68387ec525
Merge pull request #84 from bvhoof/CalibrePexFilesUpdate 
calibrepex: file copy fix
 2020-07-30 08:40:35 -07:00
Hunter Nichols c6f2edc20d Changed warning message for multiport analytical characterization. 2020-07-29 19:50:06 -07:00
mrg 64d61f4d56 Merge remote-tracking branch 'private/dev' into dev 2020-07-29 12:16:41 -07:00
mrg f23d2e36a7 Don't obstruct control logic signals with dffs when no column mux. 2020-07-29 10:31:18 -07:00
mrg 8a2fa90cd5 Merge remote-tracking branch 'private/dev' into dev 2020-07-29 10:11:26 -07:00
mrg 2fa561f98f Local bitcell array edits. Skip test by default. 2020-07-29 10:08:13 -07:00
Hunter Nichols b4dafac489 Fixed issue with sen measurement not being added 2020-07-27 23:55:03 -07:00
mrg c260297366 Allow replica_bitcell_array without the replica columns for local wordlines. 2020-07-27 16:22:21 -07:00
Hunter Nichols 9ea3616260 Changed multiport characterization warning to better fit 2020-07-27 15:47:02 -07:00
Hunter Nichols c65178f86c Fixed issue with sen delay measure getting mixed with voltage checks 2020-07-27 15:43:50 -07:00
mrg 69cab42676 Add pbuf_dec gate 2020-07-27 13:59:55 -07:00
mrg 26b01e37c6 Fix pbuf test info 2020-07-27 13:59:35 -07:00
mrg 2991534d3f Drafting local bitline stuff. 2020-07-23 17:15:39 -07:00
mrg e1967dc548 Draft local and global arrays. Ensure rows before cols in usage. 2020-07-23 14:43:14 -07:00
mrg 317662d4aa Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2020-07-23 14:17:52 -07:00
mrg b7c43ae674 Fix 1w/1r example 2020-07-23 14:17:13 -07:00
jcirimel 1d9296ceb1 fix magic.py conflict 2020-07-21 11:50:25 -07:00
jcirimel df4a231c04 fix merge conflicts 2020-07-21 11:38:34 -07:00
mrg 58846a4a25 Limit wordline driver size. Place row addr dff near predecoders. 2020-07-20 17:57:38 -07:00
mrg 0ed81aa923 Removed extraneous shift from added mirroring 2020-07-20 14:11:52 -07:00
mrg 82bbacdfb5 Add data bus gap to dynamically computed channel width 2020-07-20 13:43:57 -07:00
mrg a36e89e103 Replace data flops depending on channel width 2020-07-20 13:26:05 -07:00
mrg 2ccf3aea3b Set channel route height and width (of routes, not pins) 2020-07-20 13:25:47 -07:00
mrg f87b427f76 Add parent to channel route for dumpign debug gds. 2020-07-20 12:03:25 -07:00
mrg f35848e4f8 Route col flops separately. Flip port 1 col flop for easier routing. 2020-07-20 12:02:59 -07:00
mrg 7385decbff Add channel route cyclic VCG debugging. 2020-07-20 12:02:30 -07:00
mrg 9d5d632d1a Pins may be below the channel. 2020-07-16 14:23:48 -07:00
mrg ba3d32fa0c Starting to implement minimizing channel router (not done) 2020-07-16 13:21:44 -07:00
mrg 919e6a5027 Merge remote-tracking branch 'private/dev' into dev 2020-07-15 19:47:44 -07:00
mrg c7bc01c3a9 Clean up binning. Fix mults to 1 for certain gates. 2020-07-15 17:15:42 -07:00
Bob Vanhoof ee3da91232 calibrepex: file copy fix 2020-07-15 11:50:21 +02:00
mrg bb8157b3b7 Exit on DRC not run, check for LVSDRC before running in sram_base. 2020-07-14 08:38:49 -07:00
mrg ed9d32c7bc OpenRAM 1.1.6 2020-07-13 16:26:25 -07:00
mrg e502ee02be Place before computing height of col mux. 2020-07-13 15:51:46 -07:00
mrg 2b7d89d2c1 Fix netlist_only in sky130 2020-07-13 14:59:31 -07:00
mrg e49236f8fc Default drc and lvs errors is skipped. 2020-07-13 14:08:00 -07:00
mrg 716798baae Convert all DRC and LVS routines to set member variables for drc_errors and lvs_errors. 2020-07-13 13:01:00 -07:00
mrg 2011974e01 Make drc and lvs errors a member variable. Run only once. 2020-07-13 12:49:24 -07:00
mrg a3195c0827 Add words_per_row and others in config file. 2020-07-13 12:37:56 -07:00
mrg a989ea63a0 Move magic/netgen files to tech dir 2020-07-09 11:33:14 -07:00
mrg 27166c75f0 Don't remove temp files during regular openram runs. 2020-07-03 07:00:56 -07:00
mrg 5dde466ab9 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2020-07-03 06:55:45 -07:00
mrg 282f944b2f Also write .lvs file since it can be different the .sp 2020-07-03 06:55:35 -07:00
Hunter Nichols 206b02a7ee Merge branch 'dev' into characterizer_bug_fixes 2020-07-02 18:00:41 -07:00
Hunter Nichols fb34338fdf Removed debug statements 2020-07-02 18:00:02 -07:00
Hunter Nichols 119bd94689 Fixed warnings with single port characterization. Cleaned up some signal names. 2020-07-02 15:43:23 -07:00
mrg d48f483248 Fix swapped instance bug in perimeter pins. 2020-07-01 15:10:20 -07:00
mrg bed2e36550 Simplify write mask supply via logic 2020-07-01 14:44:48 -07:00
mrg 8cd1cba818 Fix missing via in wmask driver 2020-07-01 14:44:18 -07:00
mrg c340870ba0 Channel route dout wires as well in read write ports 2020-07-01 14:44:01 -07:00
mrg bb18d05f75 Move control output via inside module instead of perimeter 2020-07-01 11:33:25 -07:00
mrg 3d0f29ff3a Fix missing via LVS issues. LVS passing for some 20 tests. 2020-07-01 09:22:59 -07:00
mrg b07f30cb9e Missing output via in control logic 2020-06-30 16:23:07 -07:00
mrg 3379f46da1 Fail unit test, but mention if LVS passes and DRC fails. 2020-06-30 16:22:44 -07:00
mrg 0a87691176 Run Calibre LVS even if DRC fails. 2020-06-30 15:27:10 -07:00
mrg c1fedda575 Modifications for min area metal. 
Made add_via_stack_center iterative instead of recursive.
Removed add_via_stack (non-center) since it isn't used.
Add min area metal during iterative via insertion.
 2020-06-30 15:07:34 -07:00
mrg 011ac2fc05 Don't route to clk to perimeter on m2 2020-06-30 13:57:45 -07:00
mrg a48ea52253 Add missing contact to vdd pins. 2020-06-30 13:26:38 -07:00
mrg 5626fd182e Extra track in data bus. Remove old code. 2020-06-30 10:58:24 -07:00
mrg eb11ac22f3 Widen pitch of control bus in bank. 2020-06-30 10:58:09 -07:00
mrg 8cedeeb3d9 Widen pitch of control bus in bank. 2020-06-30 10:57:41 -07:00
Matt Guthaus 9b939c9a1a DRC/LVS and errors fixes. 
Only enact pdb if assert fails in debug.error.
Only run drc/lvs one time in parse_info by saving result.
Cleanup drc/lvs output.
 2020-06-30 07:16:05 -07:00
Hunter Nichols 0464e2df5d Allowed bitline checks for multiple ports. 2020-06-30 01:37:52 -07:00
Hunter Nichols c289637dab Allowed sen's from multiple ports to be characterized 2020-06-29 23:18:31 -07:00
mrg 372a8a728e Off by one error in channel spacing 2020-06-29 16:47:34 -07:00
mrg 459e3789b8 Change control layers in sky130. 2020-06-29 16:23:25 -07:00
mrg bec948dcc3 Fix error in when to add vias for array power 2020-06-29 15:28:55 -07:00
mrg 4e7e0c5954 Skip test in sky130 2020-06-29 15:28:16 -07:00
Matt Guthaus e97644c424 Only do reverse lookup on valid interconnect layers since layer numbers can be shared. 2020-06-29 14:42:24 -07:00
mrg 07d0f3af8e Only copy end-cap pins to the bank level 2020-06-29 11:46:59 -07:00
mrg 1bc0775810 Only add pins to periphery 2020-06-29 10:03:24 -07:00
mrg 5f3a45b91b Compute bus size separately for ports 2020-06-29 05:54:30 -07:00
mrg 47f541df0e Fix bugs in channel route. 2020-06-28 16:58:28 -07:00
mrg 5285468380 All bitcells need a vdd/gnd pin 2020-06-28 15:09:47 -07:00
mrg 751eab202b Move row addr flops away from predecode. Route spare wen separately on lower layer. 2020-06-28 15:06:29 -07:00
mrg 051c8d8697 Only add bitcells to dummy and replica rows and columns (the perimeter) 2020-06-28 14:47:54 -07:00
mrg 709535f90f Fix right perimeter pin coordinate bug 2020-06-28 14:47:17 -07:00
mrg 225fc69420 Use preferred routing direction 2020-06-28 14:29:12 -07:00
mrg 4df02dad67 Move spare wen_dff to the right by spare columns 2020-06-28 14:28:43 -07:00
mrg bc3de9db05 Pick correct side of pin in channel route. 2020-06-28 14:28:18 -07:00
mrg 0c9f52e22f Realign col decoder and control by 1/4 so metal can pass over 2020-06-28 07:15:06 -07:00
mrg 66ea559209 Use channel for dffs all at once 2020-06-27 08:23:12 -07:00
mrg c10a6a29c0 Simplify precharge pin layer 2020-06-27 08:22:16 -07:00
mrg 609aa98c8b Move write mask pin to left of cell to avoid sense amp 2020-06-27 08:21:53 -07:00
mrg 2bd498c39c Change precharge layer to m3 2020-06-27 08:21:30 -07:00
mrg c07e20cbe4 Move mux select from li to m2 in sky130 2020-06-26 14:27:16 -07:00
mrg 94d7000717 Reduce output clutter from gds write 2020-06-26 12:16:54 -07:00
mrg f57eeb88eb PEP8 cleanup, multiple vdd/gnd support 2020-06-26 11:47:55 -07:00
mrg e23d41c1d4 PEP8 cleanup 2020-06-26 11:47:35 -07:00
mrg 567675ab31 PEP8 cleanup 2020-06-26 11:47:12 -07:00
mrg af4ed3dd6e Skip riscv func test for time sake 2020-06-26 06:50:45 -07:00
mrg d53abba479 Always route the channel route since it is it's own design. 2020-06-25 17:43:44 -07:00
mrg 76e5389c33 Change riscv func test name 2020-06-25 17:43:17 -07:00
mrg 9eb1b500ea Skip phys riscv test 2020-06-25 17:31:23 -07:00
mrg f11afaa63d Refactor channel route to be a design. 2020-06-25 17:30:03 -07:00
mrg 7220b23402 Add riscv unit tests 2020-06-25 15:34:18 -07:00
mrg 66df659ad4 Col decoders are anything not bitcell pitch. 2020-06-25 14:25:48 -07:00
mrg f84ee04fa9 Single bank passing. 
Parameterized gate column mux of dff height.
End-cap only supply option instead of no vdd in bitcell.
 2020-06-25 14:03:59 -07:00
mrg ee0a003298 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2020-06-25 08:57:37 -07:00
jcirimel 5941e01b51 add missing parens 2020-06-25 08:02:08 -07:00
jcirimel 59562f2b92 move accuracy_requirement from techfile to config 2020-06-25 06:44:07 -07:00
jcirimel 812cf11e95 Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into dev 2020-06-25 06:32:29 -07:00
jcirimel 57b6d49edb fix pinv size bining 2020-06-25 06:32:07 -07:00
mrg da900b89ba Only expand implants in sky130 2020-06-24 13:48:30 -07:00
mrg ba92467fec Add no well enclosure for techs without wells 2020-06-24 12:07:47 -07:00
mrg 6c523a7556 use add_enclosure for npc contacts 2020-06-24 11:55:44 -07:00
mrg e694622f28 use add_enclosure to extend implants 2020-06-24 11:54:59 -07:00
mrg 4bc3df8931 Add get_tx_insts and expand add_enclosure 2020-06-24 11:54:36 -07:00
mrg 93d65e84e1 Fix power pin layer problems in delay line 2020-06-24 10:26:49 -07:00
mrg 98ec9442c6 Add npc enclosure for pnand2, pnand3, pnor2 2020-06-24 10:00:00 -07:00
mrg 1340908330 Remove fudge factor for pin spacing 2020-06-24 09:24:26 -07:00
mrg cddb16dabc Separate active and poly contact to gate rule 2020-06-24 09:17:39 -07:00