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OpenRAM
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2732 Commits

Author SHA1 Message Date
mrg 1de545fc8e Fix row and col cap custom names by adding default. 2020-11-03 13:32:15 -08:00
mrg 29ac541b28 Refactor dynamic cell name to utilize base class 2020-11-03 13:18:46 -08:00
mrg a128e0501e Use cell_name in col and row caps too. 2020-11-03 12:10:18 -08:00
mrg 1890385be1 Use custom cells when needed. 2020-11-03 11:58:25 -08:00
mrg 87419bd640 Fix bitcell and pbitcell with different cell names 2020-11-03 11:30:40 -08:00
mrg cb3e9517bb Use cell_properties to override cell names 2020-11-03 07:06:01 -08:00
mrg da721a677d Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
mrg 8c4584daa1 Missing import fix. 2020-11-03 06:09:42 -08:00
mrg aec5865d71 Fix base class error 2020-11-02 17:41:14 -08:00
mrg f9787eb878 Use bitcell_base for all bitcells. Fix missing setup_bitcell call 2020-11-02 17:00:15 -08:00
mrg fa89b73ef8 PR from mithro + other changable GDS file names 2020-11-02 16:00:16 -08:00
mrg 1caecf5a69 Undo version and traceback 2020-11-02 10:44:49 -08:00
Tim 'mithro' Ansell bb164d915d Allow overriding the cell size layer name. 2020-11-02 10:03:52 -08:00
Tim 'mithro' Ansell 232f754c73 Adding traceback printing to tech file import. 2020-11-02 09:52:00 -08:00
Tim 'mithro' Ansell 95d77119c7 Add caches to GDS related functions in utils.py 
* Cache the GDS reader.
 * Cache the properties (size / pins / etc) measured from the GDS files.

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
 2020-11-02 09:52:00 -08:00
Tim 'mithro' Ansell 6514bcb4c1 Use default bitcell name if one isn't provided. 
Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
 2020-11-02 09:52:00 -08:00
Tim 'mithro' Ansell 5c1250191c Fixup the bitcell.py to make subclassing work. 
Read in the GDS properties inside the __init__ method.

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
 2020-11-02 09:51:54 -08:00
mrg 029f655c1b Merge remote-tracking branch 'private/dev' into dev 2020-10-30 16:01:38 -07:00
mrg bd9bac6635 Fixed nominal_corner_only parameter. 2020-10-30 15:52:07 -07:00
mrg da9ed5494c Merge remote-tracking branch 'private/dev' into dev 2020-10-29 17:46:33 -07:00
mrg 857f5cb136 Fix copy pasta: decoder to predecode 2020-10-28 15:46:10 -07:00
mrg ae0f4fe682 Fix spice model bin parameter error 2020-10-28 10:39:54 -07:00
mrg 00cb8a28d9 Fix supply layer query 2020-10-28 10:36:13 -07:00
mrg f6c5f48b4c Default channel route is true 2020-10-28 10:31:05 -07:00
mrg acfec369d6 Add ptx cell properties 2020-10-28 09:54:15 -07:00
mrg 25495f3d94 getattr for bank parameters 2020-10-28 09:21:36 -07:00
mrg 611a4155b9 Add initial custom layer properties. 2020-10-27 15:11:04 -07:00
mrg 5bff641c0a Multiport constants can't be static 2020-10-27 09:28:21 -07:00
mrg 575f504e4b Remove static method call 2020-10-27 09:26:40 -07:00
mrg 07ef43eaf8 Convert design class data to static 2020-10-27 09:23:11 -07:00
mrg f23fe07893 Add custom layers without defaults 2020-10-26 16:37:00 -07:00
mrg dc991cbcab Use pin of pgate to figure out supply layer. 2020-10-26 15:54:16 -07:00
mrg 38ba5fc10d Use pin of pgate to figure out supply layer. 2020-10-26 15:53:22 -07:00
mrg b45a7902c0 PEP8 cleanup 2020-10-26 13:13:38 -07:00
mrg b20036a867 Merge remote-tracking branch 'private/dev' into dev 2020-10-25 16:25:21 -07:00
mrg cae41c63f0 Merge branch 'spmodels' into dev 2020-10-23 16:23:12 -07:00
mrg b4ebbdd5df Require either device models or device library. Remove sky130 flag. 2020-10-23 14:07:26 -07:00
mrg f97ae723f0 Remove extraneous config files. 2020-10-23 13:56:27 -07:00
mrg cbf9c48504 Names in skiptests changed. Reduce grid router verbosity. 2020-10-23 09:22:59 -07:00
mrg dcd29214bc Temp fix to use old device names during Calibre LVS. 2020-10-21 17:05:48 -07:00
Hunter Nichols 12a8531248 Allowed for OPTS writeback of words_per_row if automatically generated during generation. 2020-10-21 03:02:39 -07:00
mrg 3d5c73709b Merge branch 'dev' into spmodels 2020-10-19 14:49:07 -07:00
mrg 9c6af8937d Merge remote-tracking branch 'private/dev' into dev 2020-10-16 17:00:05 -07:00
mrg 7da3653ce5 Only output wmask to lib file in w or rw ports. 2020-10-16 16:59:51 -07:00
mrg 5268ec547b Merge remote-tracking branch 'private/dev' into dev 2020-10-16 16:51:50 -07:00
mrg 3295a813d6 Don't use single slew for nominal corner 2020-10-16 16:51:28 -07:00
mrg db1bcd0774 Merge remote-tracking branch 'private/dev' into dev 2020-10-16 13:54:43 -07:00
mrg 35c91168f7 Add load/slew scale option to config files 2020-10-16 13:52:36 -07:00
mrg 804814d18d Add bitlines to dummy modules 2020-10-16 13:43:56 -07:00
mrg 20be7caf98 Make conditional wl and bl for dummy rows/cols. 2020-10-15 13:56:37 -07:00
mrg af40f3077c Change sky130 device cards to start with X 2020-10-15 13:56:10 -07:00
mrg b4f293b311 Merge branch 'dev' into spmodels 2020-10-15 09:46:16 -07:00
mrg 6a1f12b62d Refactored to utilize OOP 2020-10-13 11:07:31 -07:00
mrg 68d74737f7 Different bitcell and array supply pins 2020-10-13 07:41:21 -07:00
mrg 555e776712 Merge branch 'dev' into spmodels 2020-10-13 06:41:26 -07:00
jcirimel 05667d784f move sky130 specific stuff to tech module lib 2020-10-13 04:48:10 -07:00
mrg fcb7f42e48 Remove split_wl 2020-10-12 17:27:20 -07:00
mrg ca2ce8b070 Default bitcell opt1 2020-10-12 17:08:32 -07:00
mrg 6b56c833df Merge branch 'dev' into spmodels 2020-10-12 15:51:40 -07:00
mrg ef310970bf Use new Google PDK lib 2020-10-12 15:46:11 -07:00
mrg a5e8818014 OpenRAM v1.1.7 
Global and local wordlines.
Many updates all around.
 2020-10-12 09:02:38 -07:00
mrg c3d6be27be Fix argument name bug for remove wordlines 2020-10-08 16:58:38 -07:00
mrg 3648401e67 Remove another boundary subcell 2020-10-08 16:58:19 -07:00
mrg 8d5db50062 Fix missing update for left RBL offset 2020-10-08 16:40:53 -07:00
mrg b0b15e8151 Fix indent bug that failed to create rbl wl pin labels. 2020-10-08 15:28:01 -07:00
mrg 01fe02bd90 Fixes to replica bitline array. 
Copy pasta error for right dummy column offset.
Put end_caps in try/except block.
PEP 8 formatting
 2020-10-08 14:53:44 -07:00
mrg 03e1b9c50d Clean up custom cells 2020-10-08 14:22:09 -07:00
mrg 8a9bf2d4f0 Remove hardcoded structure 2020-10-08 14:07:46 -07:00
mrg 3c2e8754e0 Search all shapes for boundary rather than specify structure 2020-10-08 14:04:19 -07:00
mrg 43d2058b3c Remove temp files 2020-10-08 10:35:27 -07:00
mrg 76ab48def5 Remove temp files 2020-10-08 10:33:45 -07:00
mrg 9a0fc8047b Remove diff 2020-10-08 09:53:52 -07:00
mrg 7076c376e0 Remove log from branch 2020-10-08 09:53:17 -07:00
jcirimel 1e7ae06b7e fix extra wl in col end, work on bring wl pins out to row end array, TODO: mirror alternating row end 2020-10-08 05:32:03 -07:00
jcirimel d40c3588ed no wl for col end 2020-10-08 03:34:16 -07:00
jcirimel 4a1a7e637e merge in dev 2020-10-07 11:54:07 -07:00
mrg 483f6b187c RBL driver supply location differs for sky130 and other techs 2020-10-06 16:47:32 -07:00
mrg c2629edc1b Allow 16-way column mux 2020-10-06 16:27:02 -07:00
mrg 27d921d2db Fix run-time bug for duplicate instance check 2020-10-06 16:26:35 -07:00
mrg ba432669a1 Add various riscv examples 2020-10-06 16:25:44 -07:00
jcirimel 13e2a9f5f7 fix missed self.left_rbl refactor 2020-10-06 05:11:15 -07:00
jcirimel 888646cdf9 merge in wlbuf and begin work on 32kb memory 2020-10-06 05:03:59 -07:00
mrg a145a37cf7 PEP8 fixes in regress.py 2020-10-05 15:56:12 -07:00
mrg cb35c0aff4 Add command line -j option for number of threads. 2020-10-05 15:49:00 -07:00
mrg da83824a70 Merge branch 'wlbuffer' into dev 2020-10-05 15:33:54 -07:00
mrg c4952ca8be Skip full sram pex test too slow 2020-10-05 13:51:20 -07:00
mrg 9fe6358569 Change .spinit to .spiceinit 2020-10-05 13:50:04 -07:00
jcirimel 5246d0a93b track s8 customs modules 2020-10-05 12:10:44 -07:00
mrg 4a58f09c1c Use 4x16 decoder with dual port bitcell in tests. 2020-10-05 10:52:56 -07:00
mrg c06b02e6fc Rename single_level_column_mux to just column_mux 2020-10-05 08:56:51 -07:00
mrg f8146e3f69 Add decoder4x16 2020-10-02 15:52:09 -07:00
mrg 64cc620440 Add sram pex test 2020-10-02 14:55:10 -07:00
mrg 1fc4040607 Add pand4 and pnand4 2020-10-02 14:54:12 -07:00
mrg a62b82128c Skip riscv func test because too slow 2020-10-02 13:33:58 -07:00
mrg 1e24b780bb Initial pex sram test. 2020-10-02 13:32:52 -07:00
mrg b32c123dab PEP8 cleanup. Un-hard-code bitcell layers. Remove dead variable. 2020-10-01 11:10:18 -07:00
mrg 18c8ad265e Unique name for sram channel routes 2020-10-01 09:55:34 -07:00
mrg aaa36bf5cf Default to 2 threads only 2020-10-01 09:55:17 -07:00
mrg d315ff18e5 Add num_threads to options. PEP8 cleanup. 2020-10-01 08:07:03 -07:00
mrg b81cdab0d6 Use unique instance names for channel routes. 2020-10-01 07:43:06 -07:00
mrg 8ce23d7f17 Provide unique WL driver instance name 2020-10-01 07:17:32 -07:00
mrg bd125e2ed3 Check for duplicate instance names. 2020-10-01 07:17:16 -07:00
Matt Guthaus 2b475670f7 Check for failed result in functional simulation 2020-09-30 12:40:07 -07:00
Matt Guthaus 112d57d90a Enable riscv tests 2020-09-30 12:39:40 -07:00
mrg f4e6a8895b Update riscv unit test 2020-09-30 08:50:58 -07:00
jcirimel 7cbf456a4f sky130 rba done 2020-09-30 07:34:05 -07:00
mrg b147e8485c PEP8 formatting 2020-09-29 16:52:27 -07:00
mrg 066570bfeb Fix length of write driver 2020-09-29 16:51:55 -07:00
mrg 8e908f016e PEP8 formatting 2020-09-29 13:43:59 -07:00
mrg bca69b24e3 Optional number of functional cycles 2020-09-29 13:43:54 -07:00
mrg 54890a8d77 Add new golden data 2020-09-29 13:43:34 -07:00
mrg 449a4c2660 Exclude bitcells in other local areas not of interest 2020-09-29 12:15:42 -07:00
mrg 0c280e062a Fix func test with row/col of 0. PEP8 cleanup. Smaller global test case. 2020-09-29 11:35:58 -07:00
mrg 4b5bbe755f PEP8 cleanup. Fix cur_slew bug. 2020-09-29 11:13:58 -07:00
mrg 9032bb9869 Add global wordline delay test 2020-09-29 10:28:57 -07:00
mrg d7e2340e62 Lots of PEP8 cleanup. Refactor path graph to simulation class. 2020-09-29 10:26:31 -07:00
mrg 1eb8798bb6 Add global functional test 2020-09-28 16:12:09 -07:00
mrg b2dab486fc Add draft of path exclusion calls 2020-09-28 16:05:21 -07:00
mrg 4a987bef9a Merge branch 'wlbuffer' into dev 2020-09-28 15:51:45 -07:00
mrg 159c04a25d Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2020-09-28 15:51:35 -07:00
mrg 70c90ca7fb Replica bitcell array bbox to include unused WL gnd pins. 2020-09-28 14:49:33 -07:00
mrg 9c6d8d7aed Zjob to bottom. 2020-09-28 13:16:03 -07:00
mrg 5ab0d01779 Remove zjog and go with L shape. 2020-09-28 12:48:37 -07:00
mrg d65eb16513 Zjog the WL enable. Min driver is 1. 2020-09-28 12:24:55 -07:00
mrg 6f06bb9dd5 Create sized RBL WL driver in port_address 2020-09-28 11:30:21 -07:00
mrg 88731ccd8e Fix rounding error for wmask with various word_size 2020-09-28 09:53:01 -07:00
jcirimel 3dd72cdeac progress with rba pin mismatch 2020-09-23 08:37:32 -07:00
jcirimel 17e6e5eb16 row end col done 2020-09-23 08:02:56 -07:00
jcirimel 5c263e0001 rep col done w/o power pins 2020-09-23 06:24:52 -07:00
jcirimel 7afe3ea52c replica col arrangement done 2020-09-23 04:51:09 -07:00
jcirimel 7f8edf6d7c fix replica bitcell col 2020-09-23 00:36:08 -07:00
jcirimel efdc171b14 make split wl specific to each port 2020-09-23 00:08:34 -07:00
jcirimel fb6a665514 removed references to technology name 2020-09-22 18:33:03 -07:00
jcirimel de33ab3761 fix single port bitcell pattern 2020-09-22 15:08:53 -07:00
mrg c7d32089f3 Create RBL wordline buffer with correct polarity. 2020-09-17 14:45:49 -07:00
jcirimel 559dfbc7a6 single port bitcell array done 2020-09-16 05:46:14 -07:00
mrg 392afd4d4b Add unit test for hierarchical wordline. 2020-09-15 13:46:21 -07:00
mrg 11f2b6b809 Do not do final verification if supplies were not routed 2020-09-15 13:39:00 -07:00
mrg e7ad22ff69 Separate WL via from bitell array to avoid grounded WLs 2020-09-15 13:38:28 -07:00
mrg 5e94d76127 Make global bitline only as wide as needed rather than whole array 2020-09-15 13:24:38 -07:00
mrg aff3cd2aab Update length of control bus 2020-09-15 09:49:00 -07:00
jcirimel d22164bd48 single port progess 2020-09-14 18:11:38 -07:00
mrg f25b6ffa61 Make control bus height of port data 2020-09-14 15:42:17 -07:00
mrg 7b24d1f012 Use pins for write_driver dimensions 2020-09-14 14:42:28 -07:00
mrg 55dd4d0c47 Global bitcell array working 2020-09-14 14:35:52 -07:00
mrg deaaec1ede Fix width of write enable with spare columns 2020-09-14 13:09:45 -07:00
mrg c12720a93f Extend pin correct length in new array. 2020-09-14 12:53:59 -07:00
mrg e95ab66916 Update to space according to the bitcell array. 2020-09-14 12:05:45 -07:00
mrg 4482c63d6f Fix sense amp offset index error 2020-09-11 17:12:29 -07:00
mrg 8909ad7165 Update modules to use variable bit offsets. 
Bitcell arrays can return the bit offsets.
Port data and submodules can use offsets for spacing.
Default spacing for port data if no offsets given.
 2020-09-11 15:36:22 -07:00