12 Commits

Author	SHA1	Message	Date
Hunter Nichols	016604f846	Fixed spacing in golden lib files. Added column mux into analytical model.	2018-10-24 00:16:26 -07:00
Hunter Nichols	62439bdac6	Fixed merge conflicts with sram.py	2018-10-22 17:29:14 -07:00
Hunter Nichols	4f08062268	Added custom 1rw+1r bitcell. Testing are currently failing.	2018-10-22 17:02:21 -07:00
Matt Guthaus	ab7a83b7a5	Remove old setup.tcl and edit one in tech dir	2018-10-20 15:20:15 -07:00
Matt Guthaus	4bf1e206e2	Merge branch 'dev' into supply_routing	2018-10-17 09:47:18 -07:00
Michael Timothy Grimes	e60deddfea	adding 6T transistor size parameters to tech files for use in pbitcell.	2018-10-17 07:28:56 -07:00
Matt Guthaus	4932d83afc	Add design rules classes for complex design rules	2018-10-12 09:44:36 -07:00
Matt Guthaus	c0ffa9cc7b	Clean up magic config file copying. Add warning for missing files.	2018-10-05 08:36:12 -07:00
Matt Guthaus	b3fa6b9d52	Make setup.tcl file a technology file	2018-10-05 08:30:25 -07:00
Matt Guthaus	8d2804b9cb	Supply router working except: ... Off grid pins. Some pins do now span enough of the routing track and must be patched. Route track width. Instead of minimum width route, it should be the track width.	2018-09-18 12:57:39 -07:00
Matt Guthaus	f4389bdd8f	Add extra track spacings in some routes.	2018-09-13 14:12:24 -07:00
Matt Guthaus	63d0523228	Added scn4m_subm. ... Added scn4m_subm files (instead of scn4me_subm). Fixed missing cifoutput/cifinput in magic tech file and gds files. Fixed incorrect M3/via3/M4 design rules.	2018-09-13 12:53:35 -07:00