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OpenRAM
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199 Commits

Author SHA1 Message Date
Matt Guthaus b8a3bc9b1a Space hier decoder input connections along rails to avoid conflicts 2018-07-18 10:21:58 -07:00
Matt Guthaus ef60b02a81 Add vdd/gnd pins to dff_array 2018-07-17 15:01:31 -07:00
Matt Guthaus 6133d54684 Fix spacing between adjacent decoders 2018-07-17 15:01:16 -07:00
Matt Guthaus ffc866ef78 Single bank working except for channel routing error in 4-way case. 2018-07-17 14:40:04 -07:00
Matt Guthaus 7a69fc1bca Add col addr routing and data routing 2018-07-17 14:24:44 -07:00
Matt Guthaus 0175c88a16 Convert predecodes to use create_bus api 2018-07-17 14:23:06 -07:00
Matt Guthaus ac22b1145f Convert bank to use create_bus routines. 
Modify control logic to have correct offset in SRAM.
 2018-07-16 14:13:41 -07:00
Matt Guthaus afcc3563ae Add new supplies to RBL and control logic 2018-07-16 12:58:15 -07:00
Matt Guthaus 93e830e800 Add new supplies to replica bitline 2018-07-16 10:49:43 -07:00
Matt Guthaus 3bbb604504 Add new power supplies to delay chain 2018-07-16 10:19:52 -07:00
Matt Guthaus f3ae29fe0b Getting single bank to work reliably. Removed tri_gate from bank 
for now. Will add it in multibank arrays only. Not needed for
separate DIN and DOUT ports.
 2018-07-13 14:45:46 -07:00
Matt Guthaus 25cf57ede5 Push create bus functions down into layout class. 2018-07-10 10:06:59 -07:00
Matt Guthaus 98f1914e9f Fix width of decoder with new input bus. Bank tests work again. 2018-07-10 09:31:41 -07:00
Matt Guthaus 94db2052dd Consolidate metal pitch rules to new design class 2018-07-09 15:42:46 -07:00
Matt Guthaus 2e5d60ae87 Fix input height error for input rail pins 2018-07-09 14:45:27 -07:00
Matt Guthaus e60d157310 Add input pin rails to hierarchical decoder for easier connections at SRAM level. 2018-07-09 13:16:38 -07:00
Matt Guthaus af84742c19 Simplify m2 pitch calculation 2018-07-09 09:57:57 -07:00
Matt Guthaus cc815f4c33 Fix sense amp spacing after modifying index to be increment by one. 2018-06-29 15:30:17 -07:00
Matt Guthaus 99fe3b87fe Remove temp file. Fixing indexing of sense amp outputs. 2018-06-29 15:22:58 -07:00
Michael Timothy Grimes e19a422696 simplfying calculations in pbitcell and changing pbitcell_array_test to check different port combinations 2018-05-31 17:39:51 -07:00
Michael Timothy Grimes 8f131ddb2f commiting changes from most recent pull from dev 2018-05-22 17:30:51 -07:00
Michael Timothy Grimes 766042fe69 changed case of handmade bitcell pins from upper case to lower case. Made changes in other modules that are affected by this case. Only for SCMOS for this commit 2018-05-22 14:16:51 -07:00
Michael Timothy Grimes 5e4d4bf6cd resolved conflicts with bitcell_array after PrivateRAM merge 2018-05-22 14:12:14 -07:00
Michael Timothy Grimes b5df0cc30a Merging branch with PrivateRAM dev 2018-05-18 15:15:31 -07:00
Matt Guthaus f34c4eb7dc Convert entire OpenRAM to use python3. Works with Python 3.6. 
Major changes:
Remove mpmath library and use numpy instead.
Convert bytes to new bytearrays.
Fix class name check for duplicate gds instances.
Add explicit integer conversion from floats.
Fix importlib reload from importlib library
Fix new key/index syntax issues.
Fix filter and map conversion to lists.
Fix deprecation warnings.
Fix Circuits vs Netlist in Magic LVS results.
Fix file closing warnings.
 2018-05-14 16:15:45 -07:00
Matt Guthaus 0e35937da5 Commit local changes. Forgot what the status is. 2018-05-11 09:15:29 -07:00
Michael Timothy Grimes 3971835f24 changed pbitcell_array tests in regards to addition of read/write ports in pbitcell 2018-05-10 09:40:43 -07:00
Matt Guthaus 875eb94a34 Move bank select below row decoder, col mux, or col decoder. 2018-04-23 12:17:16 -07:00
Matt Guthaus e04f53dc27 Rotate via 2018-04-23 09:18:34 -07:00
Matt Guthaus 269d553857 Move sense amp to tri gate routing to M3... not ideal. 2018-04-23 09:14:18 -07:00
Matt Guthaus cd502895c4 Undoing last change. 2018-04-23 08:48:50 -07:00
Matt Guthaus 8ce3809cad Divide index 2018-04-20 17:09:15 -07:00
Matt Guthaus ed76a784d2 Remove power rails and ring. 2018-04-20 15:51:19 -07:00
Matt Guthaus 19a957a57c Fix unattached label on sense amp out by changing layer. 2018-04-20 15:48:38 -07:00
Matt Guthaus d734c05b71 Fix missing vdd pins and fix routing between sense amp, bitcell array and column mux. 2018-04-20 15:47:21 -07:00
Matt Guthaus 929122b6dc Change default to scmos. Refactor add column mux. 2018-04-20 12:52:41 -07:00
Matt Guthaus c75eafe085 Fix some errors 2018-04-18 09:37:33 -07:00
Matt Guthaus 63a8f7c653 Remove m2 from write driver 2018-04-16 16:15:35 -07:00
Matt Guthaus bb1ec63c4f Removed msf data flop from bank 2018-04-16 16:03:46 -07:00
Matt Guthaus 1ba87c88f5 Remove supply rails in decoder 2018-04-16 15:59:52 -07:00
Matt Guthaus 13adfc3724 Add bank ground routing 2018-04-16 10:15:36 -07:00
Matt Guthaus 3fe4578feb Change stages of delay to odd 2018-04-16 10:15:15 -07:00
Matt Guthaus 70c92c27ef Supply to M3 for bank select logic 2018-04-11 16:55:09 -07:00
Matt Guthaus 010a187545 Remove dead logic 2018-04-11 16:54:55 -07:00
Matt Guthaus e038561b4a Move supply to M3 in wordline driver 2018-04-11 16:23:45 -07:00
Matt Guthaus 6640d3491d Tri gate and array supply to M2 and M3 2018-04-11 15:11:47 -07:00
Matt Guthaus 1e36e8e20c Fix ms_flop array for M3 supplies 2018-04-11 14:25:04 -07:00
Matt Guthaus 873be38e15 Add M3 pins on dff_buf array 2018-04-11 12:09:15 -07:00
Matt Guthaus 4971dde316 Rename pin variable 2018-04-11 12:08:57 -07:00
Matt Guthaus fa59b3d33d Copy predecoder supply pins 2018-04-11 11:56:41 -07:00
Matt Guthaus 1afb0a1d86 Add M3 supply vias to decoder. 2018-04-11 11:47:37 -07:00
Matt Guthaus 3ba90c035f Don't bring M2 rails over supply to allow supply connections. 2018-04-11 11:47:22 -07:00
Matt Guthaus f3baf48c22 Rotate vias in hierarchical predecodes 2018-04-11 11:12:32 -07:00
Matt Guthaus 424eb17921 Add M3 pins to hierarchical predecodes 2018-04-11 11:10:34 -07:00
Matt Guthaus 4f8ab78ee2 Change write driver supply pins to M2 2018-04-11 09:29:54 -07:00
Matt Guthaus a6c2e77bcf Move precharge and column mux cells to pgate directory. 
Move gnd to M3 in column mux.
Create column mux cell unit test.
 2018-04-06 17:15:14 -07:00
Matt Guthaus 91e342e4c9 Move precharge vdd pin to left edge. 2018-04-04 15:03:29 -07:00
Matt Guthaus a772217172 Route precharge_array vdd in M3 2018-04-04 13:49:55 -07:00
Matt Guthaus f9916f9f43 Route precharge vdd to M3 2018-04-04 13:34:56 -07:00
Michael Timothy Grimes 7f46a0dead merging changes in bitcell.py 2018-04-03 09:46:12 -07:00
Matt Guthaus a0bf5345f8 Mostly working for 1 bank. 2018-03-23 08:14:26 -07:00
Matt Guthaus 97c08bce95 Add dffs to control logic. Rename layout pin segment/rect functions for consistency. Redo gnd/vdd pins in control. 
Shift s_en buffers even with other cells.
 2018-03-23 08:14:09 -07:00
Matt Guthaus 696433b1ec Add bank_sel to bank_select module as input. 
Remove reference to control in sram.
Add dff_buf_array to options.
Added inverted DFF
Add variable height pinvbuf
 2018-03-23 08:13:39 -07:00
Matt Guthaus 5bf915a232 Detect via size for power ring. 2018-03-23 08:13:28 -07:00
Matt Guthaus ed2fa10caa Use LSB for column mux. 
Detect via size for power ring.
 2018-03-23 08:13:20 -07:00
Matt Guthaus bab92fcf38 Rework hierarchical decoder to not be folded. Remove address from central bank bus and access via side pins now. Eight way column mux now works. 2018-03-23 08:13:20 -07:00
Matt Guthaus 1f81b24e96 Single bank passing DRC and LVS again. 
Unfold hierarchical decoder to improve routability.
 2018-03-23 08:13:10 -07:00
Matt Guthaus b867e163a6 Move label pins to center like layout pins. 
Rework of control logic with vertical poly. Passes DRC/LVS.
Single bank passing DRC.
 2018-03-23 08:12:59 -07:00
Matt Guthaus 8ca9ba4244 Recreate delay chain and RBL to have vertical poly only. 2018-03-23 08:12:47 -07:00
Matt Guthaus ed8eaed54f Reworking control logic for veritcal poly. Rewrote delay line. Rewrote buffered-DFF array. 2018-03-23 08:12:47 -07:00
Matt Guthaus c020d74f26 Add dff_buf and dff_array modules. 2018-03-23 08:11:51 -07:00
Michael Timothy Grimes 0cc077598e Added member functions to bitcell.py and pbitcell.py for use in bitcell_array.py. bitcell_array now used only one function for every type of bitcell. 2018-03-15 12:02:38 -07:00
Michael Timothy Grimes 65735c08e2 fixed bitcell_array to work with different sized pbitcells, changed sizing in pbitcell to minimize space between inverters 2018-03-08 16:39:26 -08:00
Michael Timothy Grimes 0ea5d0b6a7 making changes to bitcell_array to account for the addition nets from the multiported bitcells 2018-03-06 17:03:21 -08:00
Matt Guthaus a2514878c1 Simplify dff array names of 1-dimension. Add ports on metal2. 2018-03-05 16:22:35 -08:00
Matt Guthaus 54f245cb9f Fix capitalization of pins in dff_array 2018-03-05 14:04:34 -08:00
Matt Guthaus 4205a6a700 Connect bank supply rings in sram.py. 2018-03-05 13:49:22 -08:00
Matt Guthaus 0c203c1c7e RBL width is max of delay chain or bitcell load. 2018-03-05 10:23:13 -08:00
Matt Guthaus 98fb1173df Move bank select logic to a self contained module. 2018-03-05 10:22:51 -08:00
Matt Guthaus 0f721a3d40 Add vdd and gnd rails around bank structure. 2018-03-04 17:53:22 -08:00
Matt Guthaus 8d9b79dfd8 Add dff_buf for buffered flop arrays. 2018-03-04 16:13:10 -08:00
Hunter Nichols d0dcd9f34b Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality. 2018-03-01 23:34:15 -08:00
Hunter Nichols e6d6680da1 Fixed conflict in delay.py 2018-02-27 13:02:22 -08:00
Hunter Nichols d0e6dc9ce7 First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level. 2018-02-26 16:32:28 -08:00
Hunter Nichols 62ad30e741 Added initial version of analytical power esitmation. Loops through instances but power estimate is not accurate. 2018-02-22 19:35:54 -08:00
Hunter Nichols beb7dad9bc Added corner paramters to power functions. This commit does not compile (sorry) 2018-02-22 00:15:55 -08:00
Hunter Nichols d4a0f48d4f Added power calculations for inverter. Still testing. 2018-02-21 19:51:21 -08:00
Hunter Nichols 179a27b0e3 Added some power functions. 2018-02-20 18:22:23 -08:00
mguthaus 28fe49d069 Change RBL to allow stages and FO for configuration 2018-02-16 11:51:01 -08:00
mguthaus 1297cb4e40 Convert dff to VTG transistors in 45nm. Correct pin order in dff library cell. 2018-02-16 10:40:05 -08:00
Matt Guthaus 2e3e95efda Change ratio of delay line and RBL size. Need to tune it better automatically. 2018-02-14 16:50:08 -08:00
Matt Guthaus 9559421ca8 Connect dff array clk in rows and columns. 2018-02-14 16:46:26 -08:00
Matt Guthaus 2d87dcda46 dff array done except for clock net 2018-02-14 16:03:29 -08:00
Hunter Nichols 8ea384a761 Fixed merging issues with power branch 2018-02-14 15:21:42 -08:00
Matt Guthaus 0804a1eceb Add new DFF. Create DFF module. Start dff_array, not tested. 2018-02-14 15:16:28 -08:00
mguthaus 767990ca3b Update golden lib tests. Add new generic SCMOS models. Fix tech error with new msflop_in_cap name. 2018-02-13 15:54:50 -08:00
Matt Guthaus f457091bba Fix typo in precharge. 2018-02-12 15:34:01 -08:00
Matt Guthaus e32b0b8f7a Change precharge input from clk to en 2018-02-12 15:32:47 -08:00
Matt Guthaus 7100d6f904 Organize top-level files into subdirs. 2018-02-09 10:25:24 -08:00