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OpenRAM
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3917 Commits

Author SHA1 Message Date
Bugra Onal 6bdcdb8f37 Merge branch 'dev' into char 2023-02-21 13:00:47 -08:00
samuelkcrow ad4b4f66dc use capped array to create banks 2023-02-21 09:58:46 -08:00
samuelkcrow 3a8e29ce77 Merge remote-tracking branch 'origin/dev' into no_rbl 2023-02-20 22:11:02 -08:00
samuelkcrow 52dcd81a08 use left_rbl instead of rbl to calculate replica column mirroring (column offset) 2023-02-20 17:28:24 -08:00
Eren Dogan b37711e643 Merge branch 'dev' into deploy_pip 2023-02-20 14:08:20 -08:00
Bugra Onal 3b69cafde7 Update Xyce char tests 2023-02-17 19:15:14 -08:00
mrg c07268d297 Disable power routing on some freepdk45 tests for issue 36 2023-02-17 17:00:04 -08:00
Eren Dogan d8a169e79f Reenable tests 2023-02-17 14:56:52 -08:00
Bugra Onal 4436c61a39 discard if precharge delay is captured 2023-02-17 14:35:09 -08:00
Bugra Onal c8a06a1317 Properly trim wrapped instances 2023-02-17 14:27:15 -08:00
Eren Dogan d3da632dc1 Fix typo in model delay test 2023-02-17 13:34:02 -08:00
Eren Dogan a7582c05dc Disable failing tests 2023-02-17 10:42:31 -08:00
Bugra Onal 7a62ec0030 Fixed typo 2023-02-16 19:36:14 -08:00
Bugra Onal 9002a8ac70 Merge branch 'dev' into char 2023-02-14 15:05:27 -08:00
Bugra Onal 4ec2dd2d1f Format fixes 2023-02-14 12:44:57 -08:00
Bugra Onal b70f919a2b Characterize only nom corner 2023-02-14 12:01:14 -08:00
samuelkcrow 51a7161cd7 fix mirroring of cap cells in cap rows 2023-02-14 10:59:00 -08:00
samuelkcrow 2565305158 fix positional getters 2023-02-13 18:45:21 -08:00
samuelkcrow 8d6d8f2f8c revert variable names to those inherited from bitcell base array 2023-02-13 18:45:21 -08:00
Eren Dogan 78e84ee8df Add version file 2023-02-07 10:30:48 -08:00
samuelkcrow 2948b08e66 copy rbl default values logic from lower array modules 2023-02-06 20:04:54 -08:00
samuelkcrow 796b1913cf fix typo in wordline var 2023-02-06 20:01:49 -08:00
samuelkcrow c256a5eb44 fix coppied functions from replica array to work correctly in capped array 2023-02-06 19:57:42 -08:00
samuelkcrow 4a22c5c56f add instance offset to capped array offset getters 2023-02-06 19:40:37 -08:00
samuelkcrow 92a9a1729e untested update to get_cell_name function used by characterizer 2023-02-06 19:19:02 -08:00
Bugra Onal 39104fa9d8 Delay measure always measure from clk neg edge 2023-02-06 14:13:56 -08:00
samuelkcrow 3dac89d041 fixing named variables passed between array modules 2023-02-04 21:06:41 -08:00
Bugra Onal 0d60c76e3b Fixed naming issues in trim_spice 2023-02-03 16:36:14 -08:00
Bugra Onal da86d50766 Guess the bitcell name format 2023-01-31 13:08:40 -08:00
Bugra Onal 5695cd69c6 removed html report requirement for sram_char.py 2023-01-31 13:08:13 -08:00
Eren Dogan dce324fc94 Fix newline for scripts 2023-01-28 22:59:08 -08:00
Eren Dogan e5fc25da6f Update copyright year 2023-01-28 22:56:27 -08:00
samuelkcrow 2f795f8068 fix height calculation bug for replica array 2023-01-26 17:38:24 -08:00
samuelkcrow cc408447b1 standardize names and content of tests in the 14_* group 2023-01-26 14:14:25 -08:00
samuelkcrow 03adf94b6a fix offsets to match original replica array, and make array translation statically sized 2023-01-26 12:31:14 -08:00
samuelkcrow 8fc93bc91a point local array to new capped array module 2023-01-24 11:09:57 -08:00
samuelkcrow ebe163c57e fix placement bug for cap cells including wrong height from replica array 2023-01-24 11:07:52 -08:00
Bugra Onal 8de3be8529 Changed the standalone characterizer interface 2023-01-23 17:48:30 -08:00
Bugra Onal 149abe1dbd expose fake_sram to library 2023-01-23 17:44:38 -08:00
Eren Dogan c613693399 Don't use Docker for unit tests 2023-01-22 18:19:56 -08:00
Eren Dogan efba4d785e Fix other commands to use conda as well 2023-01-22 18:15:38 -08:00
Eren Dogan 0c08d5da5f Search for tools in conda first 2023-01-22 18:14:48 -08:00
Eren Dogan ca03da8d95 Use conda to install the tools needed 2023-01-20 15:34:45 -08:00
Bugra Onal 817dc8a063 Guess the bl format 2023-01-20 12:50:09 -08:00
Bugra Onal a7cbf254be Merge branch 'dev' into char 2023-01-19 12:18:38 -08:00
Bugra Onal 7fdc5cc782 modify char to work with older macro 2023-01-19 11:39:16 -08:00
samuelkcrow 5573c6b241 fix pin shape issue 2023-01-18 22:44:32 -08:00
samuelkcrow d460eacfcc standardize rbl arguments interface 2023-01-18 22:43:37 -08:00
samuelkcrow 78c4ba5fc0 clean up comments 2023-01-18 21:01:30 -08:00
samuelkcrow 7021b80506 remove unused side argument from side routing functions 2023-01-18 20:36:36 -08:00
samuelkcrow 8522f32e43 radically simplify unused wordline routing code... bit of a facepalm tbh 2023-01-18 20:32:40 -08:00
samuelkcrow 78cabf9ca3 make capped array name more descriptive and add x mode to tests 2023-01-17 10:20:16 -08:00
samuelkcrow b5cddb9394 fix remaining lvs issues by adding an offset to pins gotten from subinstances and appropriately grounding wls in cap cells 2023-01-16 17:54:17 -08:00
samuelkcrow 29c79abaf8 move layout pins when copying them 2023-01-15 20:33:38 -08:00
samuelkcrow d8e0f4275d fix capped array after merge with dev 2022-12-14 14:20:54 -08:00
samuelkcrow f651b484c5 fix capped array tests after dev merge 2022-12-14 08:48:12 -08:00
samuelkcrow 6a8a76dd23 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into no_rbl 2022-12-14 08:13:08 -08:00
samuelkcrow 119bcb9197 route unused wordlines (still failing lvs) 2022-12-14 08:12:55 -08:00
Bugra Onal 8a67626e55 add back the characterizer to save function 2022-12-13 08:32:44 -08:00
Bugra Onal db85e8ecd6 standalone char and func 2022-12-13 07:53:58 -08:00
mrg 7ddb1a39dc Line wrap output spice subckt and instance lines at 80 characters. 2022-12-12 13:58:30 -08:00
samuelkcrow d224c06b25 placement positions problem fixed, incorrect w,h calculations were the problem 2022-12-10 19:03:55 -08:00
Eren Dogan fe81bbfd7e Fix paths in library usage tests 2022-12-02 20:28:14 -08:00
Eren Dogan 529dbb48c4 Fix sram creation in factory 2022-12-02 20:27:55 -08:00
Eren Dogan 6a4f6cbbed Move sram and sram_config to openram namespace 2022-12-02 15:28:06 -08:00
Eren Dogan fe0826d07c Add unit tests for library usage 2022-12-02 13:04:54 -08:00
Eren Dogan b40a17f4a5 Fix log file for sram_compiler tests 2022-12-02 13:00:12 -08:00
Eren Dogan 7396899769 Add empty build_graph() for dummy bitcells 2022-12-02 12:14:40 -08:00
samuelkcrow 68fb4e3c63 introduced some other bugs but scmos tiling is correct 2022-12-02 09:42:33 -08:00
Eren Dogan 96e57507bf Add copyright check to code format test 2022-11-30 14:50:43 -08:00
Eren Dogan 175e95dd86 Delete unused scripts 2022-11-30 14:48:51 -08:00
Bugra Onal c6485277f3 New import method into memchar script 2022-11-29 14:53:02 -08:00
Bugra Onal b9f16ea490 Merge branch 'dev' into char 2022-11-29 14:50:00 -08:00
Bugra Onal 816eff711d Recover function for measures 2022-11-29 14:48:35 -08:00
Eren Dogan e15454ebb9 Make sram_config optional for sram 2022-11-29 10:33:32 -08:00
Eren Dogan a37d41b406 Fix typo 2022-11-27 16:41:28 -08:00
Eren Dogan 316f75861b Fix unit tests running on docker with a hack for now 2022-11-27 14:32:55 -08:00
Eren Dogan 2e7206343e Remove unnecessary imports 2022-11-27 13:11:10 -08:00
Eren Dogan fccdc3c45b Use library imports globally 2022-11-27 13:01:20 -08:00
samuelkcrow ac8a15acc0 fix get_replica_top and get_replica_left return values 2022-11-21 17:42:50 -08:00
Eren Dogan e718106d87 Change is_unit_test to False by default 2022-11-21 14:52:57 -08:00
Eren Dogan e821b4a75e Print info regarding which directories are being used 2022-11-10 22:24:41 -08:00
Eren Dogan f95ff3c694 Fix library path in globals.setup_paths() 2022-11-10 21:50:31 -08:00
Eren Dogan 845f32805f Change compiler name for unit tests 2022-11-06 14:05:08 -08:00
Eren Dogan 62700e4d2b Fix OPENRAM_HOME path for library 2022-11-04 15:47:38 -07:00
Eren Dogan 557b2e7459 Reorganize library files to include everything 2022-11-04 15:10:44 -07:00
Eren Dogan 740cff985a Inform user when library's tech is used 2022-11-03 22:02:05 -07:00
mrg a213d3b0f6 Merge branch 'dev' into library 2022-11-02 16:20:56 -07:00
mrg b1a88d8c8a Remove variable reference in ifdef 2022-11-02 08:02:22 -07:00
Eren Dogan dacc0acd4d Fix paths while initializing 2022-10-25 13:01:02 -07:00
Eren Dogan 92460d2080 Move the compiler script to the root 2022-10-25 12:22:57 -07:00
Eren Dogan dc9d1e00d8 Add setup files for package 2022-10-25 12:22:18 -07:00
samuelkcrow 5a82c45a33 Change how lists of BLs and WLs are named and organized for proper connection between these modules 2022-10-24 20:08:13 -07:00
mrg 9b6eb4a120 Fix whitespace 2022-10-20 16:38:23 -07:00
mrg 8fd08916a1 Move is_non_inverting graph code to bitcell_base class to work with pbitcell too. 2022-10-20 15:16:10 -07:00
mrg aeca2c6b88 Allow any definition of KEEP to keep temp files 2022-10-20 14:31:26 -07:00
samuelkcrow 55d89fbae8 copy supply pins to top level in replica array, now passing tests 2022-10-19 17:13:54 -07:00
samuelkcrow f9419e8ff7 fix self.rbls and fix handling of rbl WLs (kinda) 2022-10-17 20:51:42 -07:00
samuelkcrow a1ca7c312d remove grounded WLs from replica array 2022-10-11 11:43:26 -07:00
Bugra Onal 6603220258 Fake sram using sram class as base 2022-10-04 15:05:38 -07:00
Bugra Onal 2b79646b8f Merge branch 'dev' into char 2022-10-04 09:09:52 -07:00
Bugra Onal c6440dc16d restore netlist on memchar 2022-09-27 13:44:28 -07:00
samuelkcrow cfd52a6065 fix offsets so array ends up at 0,0 2022-09-26 14:24:16 -07:00
samuelkcrow 8bc3903a04 remove end caps from replica column (will not pass sky130 drc) 2022-09-26 14:23:09 -07:00
Bugra Onal 2d8d90952e Fix measure functions 2022-09-14 14:34:50 -07:00
Bugra Onal 214f55f8d7 Save trimmed spice and stimulus 2022-09-14 14:34:22 -07:00
samuelkcrow 37dee02161 Merge branch 'dev' into no_rbl 2022-09-13 12:34:57 -07:00
Jesse Cirimelli-Low 3b02a8846d sky130 rba passing :) 2022-09-12 16:07:00 -07:00
Bugra Onal b1e4c83373 Move measure functions from stimuli to measure 2022-09-09 12:51:53 -07:00
Bugra Onal b9dbad4750 Separate measure statements from stimulus 2022-09-09 11:48:13 -07:00
samuelkcrow 004ee3748d add option to keep tmp files when running tests with make 2022-09-08 13:40:48 -07:00
samuelkcrow f1f18b3b54 replica code working but failing lvs 2022-09-07 19:32:25 -07:00
samuelkcrow 3ef52789be first pass splitting replica array into capped and replica array modules 2022-09-07 12:39:35 -07:00
samuelkcrow fe0cfac6c8 tests for new capped array module 2022-09-07 12:39:01 -07:00
Bugra Onal fcfb9391f6 Code formatting 2022-09-01 16:19:14 -07:00
Bugra Onal 57d7a78421 Merge branch 'multibank' into dev 2022-08-30 09:19:19 -07:00
Bugra Onal 1a214a7309 Fixed utest 25 golden 2022-08-30 09:17:51 -07:00
Bugra Onal 05ab45f39b Added graph store and read functionality 2022-08-30 09:15:35 -07:00
Jesse Cirimelli-Low 11fa0777e8 add flatglob to tech file; sky130 replica col lvs working 2022-08-22 15:30:11 -07:00
Bugra Onal d3753556c1 Pin generation instead of parsing 2022-08-18 21:09:48 -07:00
Bugra Onal eceb35f205 Skip graph exclusions on memchar 2022-08-18 20:38:09 -07:00
Bugra Onal 56879bf48b Cleanup 2022-08-18 20:35:34 -07:00
Bugra Onal f0a4665953 Add top process averness 2022-08-18 20:35:02 -07:00
Bugra Onal efd6da5300 Parse pins from HTML 2022-08-18 12:54:39 -07:00
Bugra Onal 9fba946f18 Characterizer use_model set to false 2022-08-18 12:54:09 -07:00
Bugra Onal c0c15537d9 Added golden files for freepdk test 25 2022-08-18 11:04:53 -07:00
Bugra Onal 25cc08db80 Further fixes for new verilog naming convention 2022-08-18 11:03:13 -07:00
Bugra Onal a7c6406d0d Changed verilog file naming convention 2022-08-18 10:36:54 -07:00
Bugra Onal 1a23d156c0 remove references to bank_sel 2022-08-18 10:33:46 -07:00
Bugra Onal 242d90f543 Code format fixes 2022-08-13 13:58:53 -07:00
Bugra Onal f602c6b263 HTML parsing for fake_sram added 2022-08-12 23:29:33 -07:00
Bugra Onal aefe46394c Merge branch 'dev' into multibank 2022-08-12 21:45:26 -07:00
Bugra Onal b33c2ab96c Fixed test 25 golden files 2022-08-12 21:33:40 -07:00
Bugra Onal 6ba2a9bca7 Make sure num_wmasks is 0 when no wmask is generated 2022-08-10 16:35:39 -07:00
Bugra Onal f743b1f068 Convert to new modules format 2022-08-10 16:34:49 -07:00
Bugra Onal 623c1ac02f Convert unit test 25 to new modules convert 2022-08-10 16:33:50 -07:00
Bugra Onal dc1626879e Characterizer wmask check for write_size 2022-08-10 16:11:19 -07:00
Bugra Onal 2d849aef39 Write size updated in recompute_sizes 2022-08-10 15:36:41 -07:00
Bugra Onal bd6621cb88 Increase random value range by 1 2022-08-10 14:21:54 -07:00
Bugra Onal 3f941d2fff Copy over the CSV read function to fake_sram 2022-08-10 12:59:54 -07:00
Bugra Onal c7975e3274 Use fake sram in memchar 2022-08-10 12:22:47 -07:00
Bugra Onal ae107b635f Enable datasheet generation by default 2022-08-10 12:22:47 -07:00
Bugra Onal 2101067e4a Characterizer options 2022-08-10 12:22:47 -07:00
Bugra Onal 219b29a833 Fake SRAM and Xyce RAW file option 2022-08-10 12:22:47 -07:00
samuelkcrow 8872a3e312 add tests 2022-08-10 12:22:47 -07:00
samuelkcrow 8d1d3c0e90 disable lvs/drc in char and func scripts 2022-08-10 12:22:47 -07:00
samuelkcrow e621890f78 force netlist only mode in memchar memfunc, rename char and func scripts, add description for func script 2022-08-10 12:22:47 -07:00
samuelkcrow 3e528a3e75 log sim result after func_sim 2022-08-10 12:22:47 -07:00
mrg 2adab1ea1a Initial work on separate delay and func simulation 2022-08-10 12:14:47 -07:00
samuelkcrow ebe4393d66 reorder sram __init__() argument order for tests that rely on the order 2022-08-10 12:07:09 -07:00
samuelkcrow 34ee709c69 call create() function from sram/__init__ 2022-08-10 12:07:07 -07:00
samuelkcrow 2bbd293bf2 clarify file location message for user 2022-08-10 12:06:18 -07:00
samuelkcrow 8793dda40a characterizer and functional simulator working from command line 2022-08-10 12:06:18 -07:00
samuelkcrow e2a52ec0f3 Adding characterizer executable 2022-08-10 12:06:18 -07:00
mrg 28128157c0 Initial work on separate delay and func simulation 2022-08-10 12:06:14 -07:00
Bugra Onal 48fce6485d write_size None initialization fixed 2022-08-04 16:37:21 -07:00
Bugra Onal 2ed107f9ff Fix the total addr_size 2022-08-04 16:36:26 -07:00
Bugra Onal 0ca14a3662 Fix typo on w_en 2022-08-04 16:35:09 -07:00
samuelkcrow 1177df6193 move most of place_instances to base 2022-08-01 10:33:48 -07:00
Bugra Onal 7fe0f647ef fix 2022-07-28 17:00:16 -07:00
Bugra Onal 8f955207d3 Fixed write_size checks for characterizer 2022-07-28 16:47:29 -07:00
Bugra Onal a361d9f7bb Fixed write_size checks for None 2022-07-28 16:45:58 -07:00
Bugra Onal 6efe974d7b Delete sram_base form rebase 2022-07-28 16:02:39 -07:00
Bugra Onal 9771bb7056 Don't generate wmask and if word per line is 1 2022-07-28 15:59:28 -07:00
Bugra Onal 02d8eca640 Fix indentation 2022-07-28 15:07:19 -07:00
Bugra Onal 36e23dc80f Moved template module to new modules folder 2022-07-28 15:05:34 -07:00
Bugra Onal bac40fa630 Removed SRAM directory 2022-07-28 15:04:53 -07:00
Bugra Onal caac39c88b Added 1bank module check to the multibank test 2022-07-28 15:03:41 -07:00
Bugra Onal 3f1a5a2051 Shrunk address register in multibank verilog 2022-07-28 15:03:41 -07:00
Bugra Onal 6b5fe8a096 Changed test name for multibank verilog test 2022-07-28 15:03:41 -07:00
Bugra Onal 8f00e396cd Added unit test for multibank 2022-07-28 15:03:41 -07:00
Bugra Onal d36f74a514 Not mathcing whitespace bug fixed 2022-07-28 15:03:41 -07:00
Bugra Onal 5f45f7db15 Fixed the bad commas with post-process regex 2022-07-28 15:03:41 -07:00
Bugra Onal 9bd3f1b45a None check syntax fix 2022-07-28 15:03:41 -07:00
Bugra Onal a75951b5b1 write_size init in sram_config 2022-07-28 15:03:41 -07:00
Bugra Onal e130ba736c Fixed indent error on write_size init 2022-07-28 15:03:41 -07:00
Bugra Onal 898a1f07f5 Fixed verilog filename double extension 2022-07-28 15:03:41 -07:00
Bugra Onal a87b40e1cb Added conditional sections to template 2022-07-28 15:03:41 -07:00
Bugra Onal c1e891b2fb Multibank file generation (messy) 2022-07-28 15:03:41 -07:00
Bugra Onal 846dfc79dc modified template engine & sram multibank class 2022-07-28 15:03:41 -07:00
Bugra Onal bbcbddd934 Template section clone method 2022-07-28 15:03:41 -07:00
Bugra Onal bde4a389aa Template section clone method 2022-07-28 15:03:41 -07:00
Bugra Onal 9158e92a71 TEmplate rework 2022-07-28 15:03:41 -07:00
Bugra Onal a5728cdecc Base-verilog 2022-07-28 15:03:41 -07:00
Bugra Onal 769633a459 Base template additions 2022-07-28 15:03:41 -07:00
Bugra Onal cda3822526 Verilog Template additions 2022-07-28 15:03:41 -07:00
Bugra Onal 28c5406075 Base verilog template init 2022-07-28 15:03:41 -07:00
Bugra Onal 2b1d0bd9f7 Template module done 2022-07-28 15:03:41 -07:00
Bugra Onal 0970095415 Bank select 2022-07-28 15:03:41 -07:00
Bugra Onal 859548f19f Templatable verilog file 2022-07-28 15:03:41 -07:00
Bugra Onal f08da6acc5 Fixed globals conflict 2022-07-28 15:03:41 -07:00
Bugra Onal 30f5638b9f Replaced instances of addr_size with bank_addr 2022-07-28 15:03:41 -07:00
Bugra Onal a0c6a0ad03 Set write_size default to word_size 2022-07-28 15:03:41 -07:00
Bugra Onal 29079bd6ac Added conditional sections to template 2022-07-28 15:03:41 -07:00
Bugra Onal 24bb6f8c11 Multibank file generation (messy) 2022-07-28 15:03:37 -07:00
samuelkcrow 1c8aeaa68a fix imports 2022-07-27 11:09:10 -07:00
samuelkcrow 2ff9ea4f78 move generic functions from control_logic module to new control_logic_base module 2022-07-26 23:22:02 -07:00
mrg 5db470155e Fix print errors in code format unit test. 2022-07-26 12:20:15 -07:00
mrg 69d5731d67 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2022-07-22 13:47:19 -07:00
samuelkcrow f01e73328d remove superfluous imports from multiport test 2022-07-22 13:12:03 -07:00
samuelkcrow b82213caff use packages for imports in modules 2022-07-22 12:56:47 -07:00
samuelkcrow 480862c765 remove sys.path.append calls from tests 2022-07-22 11:24:54 -07:00
Eren Dogan 03422be48c Fix carriage return 2022-07-22 19:54:35 +03:00
Eren Dogan e3fe8c3229 Remove line ending whitespace 2022-07-22 19:52:38 +03:00
Eren Dogan 2a778dca82 Add whitespace check to code format test 2022-07-22 18:22:40 +03:00
Eren Dogan 64c72ee19d Fix typo 2022-07-22 18:15:27 +03:00
Eren Dogan 449c68ccae Fix file setup in code format test 2022-07-22 18:11:14 +03:00
samuelkcrow 75efc476f7 add remaining tests 2022-07-21 19:35:02 -07:00
samuelkcrow 5fa0689c02 fix drc error in wlen_row 2022-07-21 19:35:02 -07:00
samuelkcrow 08ac1c176a connect in pin via m2 instead of m3, passes lvs now 2022-07-21 19:35:02 -07:00
samuelkcrow 12c58b0457 use spice names for delay chain output pins in layout 2022-07-21 19:35:02 -07:00
samuelkcrow 73021be8eb copy vertical bus spacing from control_logic.py 2022-07-21 19:35:02 -07:00
samuelkcrow 2611468dd7 replace route_supply with route supplies from control_logic.py 2022-07-21 19:35:02 -07:00
samuelkcrow 9182ad7c61 add m4 spacing for route_rails same as control_logic.py 2022-07-21 19:35:02 -07:00
samuelkcrow 7f52e63aca route glitch3 to inverter on wen row 2022-07-21 19:35:02 -07:00
samuelkcrow 231dca5b51 route w_en A and B inputs via M3, fix delay chain outputs connection to vertical bus 2022-07-21 19:35:02 -07:00
samuelkcrow 74bf3770d9 move pins to m3, route in pin down to avoid m3 collision 2022-07-21 19:35:02 -07:00
samuelkcrow 7567db6fe9 add rw port unit test for delay control 2022-07-21 19:35:02 -07:00
samuelkcrow fd7a7c2564 routing mistake in route_wlen 2022-07-21 19:35:02 -07:00
samuelkcrow 1e1ec54275 fix indentation errors, typos, and missing iterator 2022-07-21 19:35:02 -07:00
samuelkcrow 3526a57864 don't route rbl to conrol logic 2022-07-21 19:35:02 -07:00
samuelkcrow 1d6bd78612 multi-delay layout pins and routing for them in control logic 2022-07-21 19:35:01 -07:00
samuelkcrow d7b1368115 all route functions except for delay 2022-07-21 19:35:01 -07:00
samuelkcrow 63ea1588c1 more consise glitch names, remove pre_sen from vertical bus, typo in glitch2 placement 2022-07-21 19:35:01 -07:00
samuelkcrow 0a3c1dd9b8 remove pre_sen entirely, move inverter to wl_en row, complete placement functions 2022-07-21 19:35:01 -07:00
samuelkcrow 7b4af87fda remove the cs_buf function call... smh 2022-07-21 19:35:01 -07:00
samuelkcrow 5edb511dab try it without pre_sen 2022-07-21 19:35:01 -07:00
samuelkcrow 71f241f660 remove remaining cs_buf functions 2022-07-21 19:35:01 -07:00
samuelkcrow 67c1560df0 forgot other place with cs_buf 2022-07-21 19:35:01 -07:00
samuelkcrow fede082b80 cs instead of cs_buf now that everything else is working 2022-07-21 19:35:01 -07:00
samuelkcrow 30b9c2fc25 remove glitch inverters from placement functions, move glitch1 to pen row 2022-07-21 19:35:01 -07:00
samuelkcrow 606260dd68 use odd number inverter chains from delay chain for delay instead of external inverters 2022-07-21 19:35:01 -07:00
samuelkcrow b9b57ab6b3 double length of delay chain as well 2022-07-21 19:35:01 -07:00
samuelkcrow 06254fae72 forgot to multiply all delay chain pinouts by 2 because of previous design that only exposed pins for even numbered inverters in delay chain... oops 2022-07-21 19:35:01 -07:00
samuelkcrow 1d0741baa4 temporariliy commenting out path code that's making simulation fail. 2022-07-21 19:35:01 -07:00
samuelkcrow ef2c9fe296 exclude rbl connection in sram base for delay control logic 2022-07-21 19:35:01 -07:00
samuelkcrow 7d4b718344 add most functions needed for delay control logic, fix multi-delay pin order issue 2022-07-21 19:35:01 -07:00
samuelkcrow 45239ca2a9 use cs_buf for sense amp on r ports instead of cs 2022-07-21 19:35:01 -07:00
samuelkcrow c4138c9f9b typo in cs buf netlist function 2022-07-21 19:35:01 -07:00
samuelkcrow 2b72fbee4e bug fix list vs set 2022-07-21 19:35:01 -07:00
samuelkcrow 11ea82e782 check delay chain pinout list, add cs_buf to control logic 2022-07-21 19:35:01 -07:00
samuelkcrow 78013d32b7 hard-code multi-delay stages 2022-07-21 19:35:01 -07:00
samuelkcrow 62a65f8053 all remaining spice for delay control 2022-07-21 19:35:01 -07:00
samuelkcrow 66502fc5dc new control logic module with no more rbl logic, added glitches so far 2022-07-21 19:35:01 -07:00
samuelkcrow b05a721fb5 spice for delay chain with all inverter outputs as pins 2022-07-21 19:35:01 -07:00
Bugra Onal 6d6063ef4e modified template engine & sram multibank class 2022-07-21 15:56:29 -07:00
Bugra Onal a497943be3 Template section clone method 2022-07-21 15:45:50 -07:00
Bugra Onal b75e1fc499 Template section clone method 2022-07-21 15:45:50 -07:00
Bugra Onal f2cd611cb8 TEmplate rework 2022-07-21 15:45:50 -07:00
Bugra Onal 988399ba73 Base-verilog 2022-07-21 15:45:50 -07:00
Bugra Onal 06c56c256e Base template additions 2022-07-21 15:45:50 -07:00
Bugra Onal 3d3a8202fe Verilog Template additions 2022-07-21 15:45:50 -07:00
Bugra Onal be9fadf1bb Base verilog template init 2022-07-21 15:45:50 -07:00
Bugra Onal 874d965edb Template module done 2022-07-21 15:45:50 -07:00
Bugra Onal 99b517d55a Bank select 2022-07-21 15:45:50 -07:00
Bugra Onal 54a012b574 Templatable verilog file 2022-07-21 15:45:50 -07:00
mrg 6707a93c3c Add fudge factor for bitcell array side rail spacings to fix DRC in freepdk45. 2022-07-20 10:27:30 -07:00
mrg 3b0533c9c7 v1.2.0 2022-07-17 19:55:05 -07:00
mrg ff7ceaf92d Fix syntax error for module scope in row/col caps. 2022-07-13 17:19:09 -07:00
mrg d92c7a634d Use packages for imports. 
Must set PYTHONPATH to include OPENRAM_HOME now.
Reorganizes subdirs as packages.
Rewrites unit tests to use packages.
Update README.md with instructions, dependencies etc.
Update sky130 module imports.
Change tech specific package from modules to custom.
 2022-07-13 15:55:57 -07:00
mrg ac86ad0e8a Move pdk installation inside docker to use Magic from docker image. 2022-06-21 12:10:15 -07:00
mrg dc9ae6cd1a Increase column width in netgen LVS scripts 2022-06-16 10:30:58 -07:00
mrg cf03454ecf Don't add wdriver_sel_n pins which aren't used. 2022-06-10 09:18:40 -07:00
mrg e744ffd6ea Move mount to shared target in openram.mk 2022-06-09 06:44:23 -07:00
mrg d30f05a1ae Update power layer on li for sky130 2022-06-08 17:19:26 -07:00
mrg 9e3a28237f Update port data test for sky130 single port 2022-06-08 17:18:53 -07:00
mrg 00ca2d45b6 Extract unique is option not command. 2022-06-08 15:06:06 -07:00
mrg 4814cf6eac Merge branch 'sky130_fixes' into dev 2022-06-08 14:27:30 -07:00
mrg 280582d4d6 Add missing via in dff array 2022-06-08 14:24:17 -07:00
mrg 76bc4e1fc2 Only do one extract. Flatten transistors since bug fixed in magic. 2022-06-08 14:23:50 -07:00
mrg ad6633ddca Update versions of tools. Fix supply bug in predecode. 2022-06-08 13:50:25 -07:00
Jesse Cirimelli-Low fbe3032246 add case for single spare col spare_wen_dff i/o 2022-05-26 12:18:47 -07:00
mrg 1bab395946 Merge branch 'sky130_fixes' into dev 2022-05-24 09:12:37 -07:00
mrg cb3d7b9d5d Add spares for sky130 unit tests. 2022-05-23 17:27:26 -07:00
mrg b84b4dab43 Fail on pin mismatch too. 2022-05-23 16:28:28 -07:00
mrg 8c85230033 Remove experimental power option. 2022-05-23 10:08:35 -07:00
mrg 51b0f125fb Add offset to 0,0 that was inadvertantly removed for router debug. 2022-05-23 09:59:41 -07:00
mrg 735d66c9f1 Start dff array supplies on first rather than second bit. 2022-05-17 15:54:54 -07:00
mrg 3e02a0e7df Update column decoder and dff array supplies 2022-05-17 15:49:50 -07:00
mrg c8905c410a Fix case where distance is zero length comparison 2022-05-17 15:49:06 -07:00
mrg f1f4453d14 Add column decoder module with power supply straps. 2022-05-17 13:32:19 -07:00
mrg 8217a84165 Uniquify overlap points during segment overlap computation. 2022-05-17 13:31:23 -07:00
mrg 9b592ab432 Fix missing hash recompute in vector class. 2022-05-17 13:30:41 -07:00
mrg bed12d2a9e pbitcell vdd/gnd are on layer m1 only. 2022-05-16 17:02:53 -07:00
mrg bdd334bce9 Add layer and directions to pbitcell 2022-05-16 16:11:13 -07:00
mrg 4be075e586 Overlap length can include a rectangle overlap. 2022-05-16 14:57:32 -07:00
mrg 3101643964 Check for no pins and fix closest pin return type 2022-05-13 14:34:26 -07:00
mrg 74c2c5ae0e Don't double prefix a name 2022-05-13 14:32:52 -07:00
mrg fbb2ea5fb6 Intersection now returns a pin_layout fixed during LEF computation. 2022-05-13 13:56:16 -07:00
mrg 4345136d1a Fix offsets for local bitcell arrays. 2022-05-13 10:46:00 -07:00
mrg 357f967a93 Leave supply routing to new helper functions. 2022-05-11 11:01:14 -07:00
mrg 8f2d787d53 Add min area metal in preferred direction 2022-05-11 10:50:32 -07:00
mrg b6c3580e24 Fix width of replica routes. Don't enclose pins if they overlap sufficiently. 2022-05-09 11:44:46 -07:00
mrg 50045e54e8 Fix a couple supply routing issues. 2022-05-03 11:45:51 -07:00
mrg f8f3f16b1f Move delay line supply strap for pin access. 2022-05-02 16:42:14 -07:00
mrg 942ab89754 Remove debug output. 2022-05-02 16:42:04 -07:00
mrg 3e48991acb Skip partial pins if they are too small to prevent DRC overlap errors. 2022-05-02 16:07:05 -07:00
mrg b1bb9151c4 Reimplement off grid pins. 
Long pins aren't accessed on end pins anymore.
Fix problem with multiple non-enclosed space causing blockages.
Add partial pin offgrid enclosure algorithm.
 2022-05-02 15:43:14 -07:00
mrg 64f2f90664 Rework replica_bitcell_array supplies 
Uses layer and direction preferences in tech file.
Places straps on left/right or top/bottom.
 2022-04-19 08:50:11 -07:00
mrg 5e546ee974 New power strapping mostly working. 
Each module uses M3/M4 power straps with pins on the ends.
Works in all technologies for a single no mux, dual port SRAM.
 2022-04-05 13:51:55 -07:00
mrg 23b5655cab Split replica_bitcell_array test 2022-03-23 15:59:29 -07:00
mrg 9f7426052d Split port_address tests 2022-03-23 14:46:41 -07:00
mrg e31bec131c Remove 1rw1r combined test and add separate tests. 2022-03-22 11:59:04 -07:00
mrg a8f50f212e Change track spacing for freepdk45 2022-03-18 16:01:57 -07:00
mrg 2bfc94fcdd Add unblocking of source and destination pins to router. 2022-03-18 14:44:13 -07:00
mrg 01a73b31e1 Fix power ring routing boundary bug. 2022-03-18 10:32:25 -07:00
mrg 7e7670581c Add some vertical/horizontal pins for sky130 only 2022-03-16 07:58:29 -07:00
mrg 229a3b5b3d By default uniquify instances based on macro name. 2022-03-11 18:01:45 -08:00
mrg 4567c2ebcd Add space after docker command. Regress to klayout v0.27.4 2022-03-10 08:37:48 -08:00
mrg e16defdae4 Add a sleep to see if problem is async one 2022-03-09 10:24:50 -08:00
mrg b841e18abd Remove breakpoint 2022-03-07 16:59:55 -08:00
mrg 2796800898 Fix bug with incorrect pitch while adding channel route trunks. 2022-03-07 16:12:20 -08:00
mrg 772fbd6f96 Remove extra well tap to save area. 2022-03-07 15:38:25 -08:00
mrg f17d661e3a Add spare column option to tests for sky130 2022-03-07 07:58:41 -08:00
mrg 4faf97005f Add even columns for sky130 to ring test 2022-03-06 12:21:09 -08:00
mrg 6eeb81b9fe Skip sky130 23_lib tests and 4096 row hierarchical decoder test 2022-03-06 11:27:13 -08:00
mrg a0f1327f5e Add odd rows to 23_lib tests 2022-03-06 11:26:18 -08:00
mrg 6da3e44b6f Split up 06_hierarchical_decoder test 2022-03-06 11:26:03 -08:00
mrg 8c911f70b9 Build changes. 
Don't pull docker since it will be build by CI.
Shuffle tests to stagger technologies and test types.
 2022-03-06 10:31:43 -08:00
mrg d69e55c2e3 Power routing changes. 
Make the power rails an "experimental_power" option and conditional.
Rename route_vdd_gnd to route_supplies everywhere for consistency.
 2022-03-06 09:56:00 -08:00
mrg 8b3c10ae79 Improvements to power routing. 
Improved the route horizontal and vertical pin functions to
create a single pin at the end.
Swapped A and B on wordline driver input for cleaner routing
in most technologies.
Fixed vertical supply routing in port_address.
 2022-03-04 15:44:07 -08:00
mrg e139b4aa81 Swap A and B pins in wordline driver. 2022-03-03 09:53:24 -08:00
mrg febf7031b1 Fix wrong power layer for min area constraint 2022-03-02 17:04:54 -08:00
mrg 7654cd7295 Allow supply pins on m4 too 2022-03-02 16:47:17 -08:00
mrg 51ba88d896 Port address with vertical power stripes 2022-03-02 16:29:43 -08:00
mrg 4fac069c3c Skip hspice tests in docker 2022-03-01 14:44:04 -08:00
mrg f7e3672c89 Route horizontal supplies in write driver. 2022-03-01 14:37:51 -08:00
mrg 0908aa9e25 Add route vertical pins 2022-03-01 14:37:09 -08:00
mrg c12c006799 Add verbose option 2022-03-01 10:50:49 -08:00
mrg 38494458e3 Fix incorrect port 1w to 1r 2022-03-01 10:44:56 -08:00
mrg c223c1ad1c Run docker pull before running all tests for regression 2022-03-01 10:33:40 -08:00
mrg 184888b370 Skip 16 way test for now 2022-02-28 12:03:01 -08:00
mrg 27b4d2edb1 Add 16 way mux SRAM tests 2022-02-28 11:53:24 -08:00
mrg 54bd022efc Rework precharge route supply horizontally 2022-02-28 11:36:10 -08:00
mrg 2520d9f590 Remove commented code in precharge array 2022-02-25 16:21:12 -08:00
mrg 7b77378927 Add layer to horizontal pin help and use in precharge 2022-02-25 10:45:25 -08:00
mrg 82c2bc329f Split bank and col mux tests. 2022-02-23 15:39:32 -08:00
mrg 5376b5bf20 Fix offset to center select signal between bitlines 2022-02-23 15:38:11 -08:00
mrg 6389d4ac82 Skip all func tests 2022-02-23 15:31:15 -08:00
mrg baf369fc96 Convert power to rails rather than pins in sense amp and precharge 2022-02-23 14:06:49 -08:00
mrg d4c14d7d19 Add horizontal pin helper function 2022-02-23 14:06:19 -08:00
mrg 5451a8d07a Don't make internal bus pins because magic will extract ports 2022-02-23 14:06:01 -08:00
mrg 6a295aeb38 Give feedback warnings in magic output 2022-02-23 13:05:03 -08:00
mrg 1742927751 Split port data tests into individual tests 2022-02-23 11:12:32 -08:00
mrg 53e4c45038 Add tap to nand in pnand 2022-02-23 09:30:31 -08:00
mrg abac5a11ab Move power supply stack to design 2022-02-18 15:02:45 -08:00
mrg 4590874ffa Merge branch 'dev' into sky130_fixes 2022-02-16 09:31:49 -08:00
Jesse Cirimelli-Low 1a0861539a Merge branch 'opc_fix' into dev 2022-02-15 14:38:20 -08:00
Jesse Cirimelli-Low a54eb90371 place decoder rail contacts at least m2 min spacing away 2022-02-15 14:37:07 -08:00
mrg a75d9fcc76 Fix failing test output of Makefile 2022-02-11 13:11:24 -08:00