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OpenRAM
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2980 Commits

Author SHA1 Message Date
mrg 8dbaa66aa5 Merge branch 'super' into dev 2020-08-12 14:25:13 -07:00
mrg 7ac4574e4f Use micron units for all simulation in sky130 2020-08-12 13:54:55 -07:00
mrg 5fc6438553 Fix pinv_dec super call 2020-08-12 13:22:28 -07:00
mrg 15c8c200f3 Undo super() in measurement abstract class 2020-08-12 12:10:12 -07:00
mrg 55814a8f74 Fix syntax errors in pgates for super edits 2020-08-12 11:15:32 -07:00
mrg 0bec6f0439 Fix SRAM to use simulation spice instead of LVS spice 2020-08-12 10:41:21 -07:00
mrg a55909930f Replace replcia_bitcell_array with new one in bank 2020-08-12 09:49:14 -07:00
mrg 8e890c2014 Replica bitcell with all the fixings 2020-08-11 15:00:29 -07:00
mrg 30976df48f Change inheritance inits to use super 2020-08-06 11:33:26 -07:00
mrg eef97ff215 Reabstracting bit and word line names. 2020-08-06 11:17:49 -07:00
mrg 037de96989 Merge branch 'dev' into wlbuffer 2020-08-05 10:37:29 -07:00
mrg 528cb07635 Merge branch 'dev' into wlbuffer 2020-08-05 10:01:43 -07:00
jcirimel 19f4e30989 change Qbar to Q_bar in freepdk45 bitcells 2020-08-04 15:21:54 -07:00
jcirimel 38648027d0 fix pinv unit test 2020-08-04 04:40:20 -07:00
jcirimel 02e65a00ef update pex to work with dev changes 2020-08-03 17:14:34 -07:00
Matt Guthaus 8ec10cacd7
Merge pull request #86 from bvhoof/dev 
Dev
 2020-08-03 10:19:10 -07:00
Bob Vanhoof 9b8ef5ef57 fix: generated pex file was not passed correctly to lib characterizer 2020-08-03 10:16:12 +02:00
Bob Vanhoof 487bb6c6e9 Merge branch 'dev' of github:VLSIDA/OpenRAM into CalibrePexFilesUpdate 2020-08-03 09:32:27 +02:00
jcirimel 3221b4ec57 update to new metal stack names 2020-07-31 05:27:19 -07:00
Bob Vanhoof dc55ededc1 fix regession tests after calibre fix 2020-07-31 12:51:34 +02:00
mrg 487027a9f2 Fix pex file names 2020-07-30 11:35:13 -07:00
mrg 8fa0065aaf Undo PR 82 changes -- broke unit test. 2020-07-30 11:09:19 -07:00
mrg a663d903c5 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2020-07-30 08:44:25 -07:00
Matt Guthaus 68387ec525
Merge pull request #84 from bvhoof/CalibrePexFilesUpdate 
calibrepex: file copy fix
 2020-07-30 08:40:35 -07:00
Hunter Nichols c6f2edc20d Changed warning message for multiport analytical characterization. 2020-07-29 19:50:06 -07:00
mrg 64d61f4d56 Merge remote-tracking branch 'private/dev' into dev 2020-07-29 12:16:41 -07:00
mrg f23d2e36a7 Don't obstruct control logic signals with dffs when no column mux. 2020-07-29 10:31:18 -07:00
mrg 8a2fa90cd5 Merge remote-tracking branch 'private/dev' into dev 2020-07-29 10:11:26 -07:00
mrg 2fa561f98f Local bitcell array edits. Skip test by default. 2020-07-29 10:08:13 -07:00
Hunter Nichols b4dafac489 Fixed issue with sen measurement not being added 2020-07-27 23:55:03 -07:00
mrg c260297366 Allow replica_bitcell_array without the replica columns for local wordlines. 2020-07-27 16:22:21 -07:00
Hunter Nichols 9ea3616260 Changed multiport characterization warning to better fit 2020-07-27 15:47:02 -07:00
Hunter Nichols c65178f86c Fixed issue with sen delay measure getting mixed with voltage checks 2020-07-27 15:43:50 -07:00
mrg 69cab42676 Add pbuf_dec gate 2020-07-27 13:59:55 -07:00
mrg 26b01e37c6 Fix pbuf test info 2020-07-27 13:59:35 -07:00
mrg 2991534d3f Drafting local bitline stuff. 2020-07-23 17:15:39 -07:00
mrg e1967dc548 Draft local and global arrays. Ensure rows before cols in usage. 2020-07-23 14:43:14 -07:00
mrg 317662d4aa Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2020-07-23 14:17:52 -07:00
mrg b7c43ae674 Fix 1w/1r example 2020-07-23 14:17:13 -07:00
jcirimel 1d9296ceb1 fix magic.py conflict 2020-07-21 11:50:25 -07:00
jcirimel df4a231c04 fix merge conflicts 2020-07-21 11:38:34 -07:00
mrg 58846a4a25 Limit wordline driver size. Place row addr dff near predecoders. 2020-07-20 17:57:38 -07:00
mrg 0ed81aa923 Removed extraneous shift from added mirroring 2020-07-20 14:11:52 -07:00
mrg 82bbacdfb5 Add data bus gap to dynamically computed channel width 2020-07-20 13:43:57 -07:00
mrg a36e89e103 Replace data flops depending on channel width 2020-07-20 13:26:05 -07:00
mrg 2ccf3aea3b Set channel route height and width (of routes, not pins) 2020-07-20 13:25:47 -07:00
mrg f87b427f76 Add parent to channel route for dumpign debug gds. 2020-07-20 12:03:25 -07:00
mrg f35848e4f8 Route col flops separately. Flip port 1 col flop for easier routing. 2020-07-20 12:02:59 -07:00
mrg 7385decbff Add channel route cyclic VCG debugging. 2020-07-20 12:02:30 -07:00
mrg 80070dff41 Move write_driver din left to avoid control signal in spare columns. 2020-07-16 14:47:14 -07:00