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OpenRAM
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3,599 Commits 4 Branches 63 Tags 78 MiB
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3150 Commits

Author SHA1 Message Date
Hunter Nichols 74b55ea83b Added a graph exclusion clear for the mux to prevent previous graph creations causing bugs. 2021-06-14 14:39:54 -07:00
Hunter Nichols 7df36a916b Added an exclusion for unused column mux paths to prevent multiple outputs paths in graph. 2021-06-14 13:51:52 -07:00
Hunter Nichols 4d22201055 Changed name of regression test since we currently only test the delay. 2021-06-14 10:57:20 -07:00
mrg 159d0ed603 Fix s_en spacing problem. 2021-06-13 15:08:05 -07:00
mrg 53107a8322 Add ring test 2021-06-13 15:03:41 -07:00
mrg d6a72aed37 Add 2x1 perimter pins to satisfy minimum area rule. 2021-06-13 15:00:46 -07:00
mrg 2e23fffadd Fix comment 2021-06-13 14:18:55 -07:00
Jesse Cirimelli-Low 73cc6b3891 uncomment 4x16 decoder 2021-06-11 18:20:36 -07:00
Jesse Cirimelli-Low bee9b07516 fix decoder routing 2021-06-11 18:19:07 -07:00
Jesse Cirimelli-Low 2e72da0e53 rotate input to rail contacts for drc 2021-06-10 14:01:28 -07:00
Jesse Cirimelli-Low 247a388ab5 Merge branch 'dev' into laptop_checkpoint 2021-06-09 18:25:45 -07:00
Jesse Cirimelli-Low 10f561648f remove hierarchical decoder vertial m1 above pins 2021-06-09 18:24:21 -07:00
mrg 8964abc2b7 Change simulator based on one in use. 2021-06-09 16:02:32 -07:00
Hunter Nichols 4ec2e1240f Merge branch 'dev' into automated_analytical_model 2021-06-09 15:45:41 -07:00
Hunter Nichols c50ffe70b3 Added more configs for model and respective data. 2021-06-09 15:42:15 -07:00
Hunter Nichols ccf98ad5a6 Added accuracy check in regression model test. 2021-06-09 13:44:42 -07:00
Hunter Nichols b6b20c1f43 Removed level 0 debug statements for bitlines naming. 2021-06-09 12:53:31 -07:00
Hunter Nichols f25dcf1b63 Fixed issue with bitline name warning occuring when no issue is present. 2021-06-09 12:52:26 -07:00
Hunter Nichols a73bfe6c2c Added more configs for model and data from scn4m_subm run. 2021-06-09 10:35:58 -07:00
mrg a1cb20878d Swap LH/HL hold times in sky130. 2021-06-08 11:14:27 -07:00
Hunter Nichols 3d82718f5a Changed neural network model to be sklearn based 2021-06-07 12:26:45 -07:00
mrg 27c6a13923 Back out drc listall count for detecting errors 2021-06-04 15:51:50 -07:00
mrg cf61096936 Merge branch 'laptop_checkpoint' into dev 2021-06-04 15:22:37 -07:00
Hunter Nichols 331e6f8dd5 Added functions for testing accuracy of current regression model and associated test. 2021-06-04 15:04:52 -07:00
Hunter Nichols 84783bbac5 Added more configs for model generation 2021-06-04 13:38:17 -07:00
Hunter Nichols 54639bbb94 Added more data for regression models 2021-06-04 13:37:21 -07:00
mrg 6643759345 Add back drc listall with correct output. 2021-06-04 11:06:39 -07:00
mrg 53791d79c8 spacing must be two extensions (one for each cell) 2021-06-04 08:56:06 -07:00
mrg cc4c6e909b Check if s_en exists before using it 2021-06-04 07:48:26 -07:00
mrg 4107c983e2 Make sure channel route is below s_en 2021-06-04 07:14:49 -07:00
mrg 537fd6eff9 Use None instead of empty string for tool names. 2021-06-01 16:41:14 -07:00
mrg 1ded978256 Change nwell from gnd to vdd. dnwell space added. 2021-06-01 15:10:55 -07:00
Hunter Nichols 0692593236 Specified line terminator in sim_data output to prevent carriage returns 2021-06-01 14:49:08 -07:00
Hunter Nichols 35ce838c8a Fixed issues with makefile with removal of prerequisite 2021-05-31 01:07:12 -07:00
Hunter Nichols 4da9d3beaf Removed config file as a prereq in makefile due to errors. Changes in config file will not result in a re-simming of that configuration now and will require a clean. 2021-05-30 23:58:24 -07:00
Hunter Nichols ccfda16ab2 Changed makefile to include okay files to indicate which configs have already been simulated for the existing models. 2021-05-30 22:19:56 -07:00
Jesse Cirimelli-Low 24b45ca2d4 use flat magic files instead of gds flatten subcell 2021-05-29 16:54:36 -07:00
Jesse Cirimelli-Low 131ca42512 merge in dev 2021-05-29 16:11:21 -07:00
Jesse Cirimelli-Low 97f43e31f0 remove breakpoint 2021-05-29 16:08:31 -07:00
mrg e944a5ec02 Use open_pdks setup.tcl if available. Set vdd/gnd/sub in run_ext.sh 2021-05-28 16:39:48 -07:00
Jesse Cirimelli-Low 6705f99855 merge in dev 2021-05-28 14:06:23 -07:00
Jesse Cirimelli-Low 1a894a99dd push bias pins to top level power routing 2021-05-28 13:41:58 -07:00
mrg 9e8d39f911 Remove debug gds dump 2021-05-28 13:31:19 -07:00
mrg d6d0df97f8 Get rid of write_size error when write_size==word_size 2021-05-28 13:06:12 -07:00
mrg 77f221d859 Separate supply pin type from route supplies option 2021-05-28 11:55:50 -07:00
mrg 013c5932a0 Valid type is tree not single 2021-05-28 11:26:41 -07:00
mrg f6587badad Improve supply routing for ring and side pins 2021-05-28 10:58:30 -07:00
Hunter Nichols da67edbde8 Changed input format for delay module in xyce delay test. 2021-05-26 20:11:30 -07:00
Hunter Nichols b3bcf48d2e Merge branch 'dev' into automated_analytical_model 2021-05-26 18:42:24 -07:00
Hunter Nichols a53c6c51ed Added sim data for freepdk45 and removed stale data 2021-05-26 18:40:46 -07:00
mrg 61221ff4fa Allow tree type 2021-05-26 17:46:41 -07:00
mrg 8bf37ca708 Connect dnwell taps to gnd 2021-05-26 17:38:09 -07:00
mrg 2b5013fd69 Config example changes 2021-05-26 16:14:48 -07:00
mrg 7736d3b927 Fix updated side pin option 2021-05-26 16:14:46 -07:00
mrg 6de5787e58 Fix offsets for ring 2021-05-26 16:14:16 -07:00
mrg e611f66767 Add dnwell 2021-05-26 16:14:16 -07:00
mrg 6493d1a7f4 Add dnwell 2021-05-26 16:14:16 -07:00
mrg cc91cdf008 Add power ring pin 2021-05-26 16:14:14 -07:00
mrg bc793ec3d8 PEP8 2021-05-26 16:13:47 -07:00
mrg 8610144ccb Fix write size warning 2021-05-26 16:13:47 -07:00
mrg e16f44cc81 Update lib file with external supply names 2021-05-26 15:34:32 -07:00
mrg d579a60382 Fix external supply names in verilog 2021-05-26 15:26:20 -07:00
mrg 7fa6c7ce0f Typo in wmask supply variable 2021-05-26 15:24:31 -07:00
mrg 4a8e0cdabb Add top-level pin functionality 2021-05-26 15:04:52 -07:00
Hunter Nichols 2f4f8ca912 Fixed conflicts in delay and elmore modules on merge with dev. 2021-05-25 15:25:43 -07:00
Hunter Nichols 52bf8d09d7 Added tech dir to model output so different tech dont overwrite the outputs of eachother. 2021-05-25 15:21:32 -07:00
Hunter Nichols 76f5578cc1 Removed path delays from characterization output to not disturb the current testing flow. 2021-05-25 15:19:27 -07:00
Hunter Nichols 23368c0fcf Updated tests and elmore model with load_slew lists. Changed naming on characterization output to not clash with testing. 2021-05-25 14:49:28 -07:00
Hunter Nichols 1488b31dce Adjusted model prediction to account for a single datafile. Adjusted unscaling data as well. 2021-05-24 12:53:51 -07:00
Hunter Nichols 53503f40d2 Changed util functions to expect multiple outputs in data. Changed train models to account for multiple outputs when reading in data. 2021-05-24 12:03:26 -07:00
Hunter Nichols a4cb539f72 Removed old sim data csvs and added a new version. Added a default check for LAS in data extraction. 2021-05-24 10:44:46 -07:00
Jesse Cirimelli-Low f9eae3fb80 route bias pisn 2021-05-24 02:42:04 -07:00
mrg 9c01e22281 Prioritize Xyce. 2021-05-21 12:05:10 -07:00
mrg f856a44376 Restrict to direct KLU solver 2021-05-21 12:04:26 -07:00
mrg fc17a1ff45 Xyce can be capital or lower case 2021-05-21 12:04:26 -07:00
mrg d51ec4fe45 Add Xyce tests 2021-05-21 12:04:26 -07:00
mrg eadf7eedc5 Prioritize Xyce to last until bugs resolved. 2021-05-21 10:01:37 -07:00
Hunter Nichols 4e40017fdc Added model configs adapted from OpenRAM Library 2021-05-20 15:26:24 -07:00
Hunter Nichols 41c8eeb23c Adjusted paths in makefile for generating data used in regression models 2021-05-20 13:05:16 -07:00
Hunter Nichols 269b698b0a Fixed issues with csv generation. Added regex parsing to determine corners from datasheet. 2021-05-18 23:41:16 -07:00
mrg 7c001732b1 Add destination file as dot file 2021-05-18 14:54:13 -07:00
mrg 191b382171 Change magic to use OPENRAM_MAGICRC if defined. 2021-05-18 13:27:11 -07:00
Hunter Nichols 36b1bc1284 Added script to extract data from datasheet output and store in CSV. 2021-05-17 14:04:20 -07:00
Hunter Nichols 0434e57609 Added target in makefile to run configs and store results in tech directory. 2021-05-17 14:03:32 -07:00
mrg 3abebe4068 Add hierarchical seperator option to work with Xyce measurements. 2021-05-14 16:16:25 -07:00
mrg 7534610cdd Add MPI capability for Xyce threading. 2021-05-14 11:45:37 -07:00
mrg 507ad9f33d Change sim threads to 3. 2021-05-14 11:45:10 -07:00
mrg 67a67111a6 Initial Xyce support. 2021-05-14 11:28:29 -07:00
mrg 3959cf73d1 Remove setup/hold measure and compute it directly. 2021-05-14 10:11:14 -07:00
mrg 9555b52aaa Remove setup/hold measure and compute it directly. 2021-05-14 10:01:10 -07:00
Jesse Cirimelli-Low 0ba229afe5 Merge branch 'dev' into laptop_checkpoint 2021-05-07 19:06:17 -07:00
Jesse Cirimelli-Low e5662180e8 single port 20 series tests running 2021-05-07 18:44:45 -07:00
Jesse Cirimelli-Low 6d8411d19f use consistent amp spacing 2021-05-07 11:29:43 -07:00
mrg d43edd95e4 Update golden tests for verilog 2021-05-06 19:56:22 -07:00
mrg 57c58ce4a5 Always route data dff on m3 stack. 2021-05-06 17:14:39 -07:00
mrg 453f260ca2 Add commented save npz file for intern 2021-05-06 17:14:27 -07:00
mrg e995e61ea4 Fix Verilog module typo. Adjust RBL route. 2021-05-06 14:32:47 -07:00
mrg c057490923 Delay chain should have same height cells as control logic to align supplies. 2021-05-05 15:45:28 -07:00
mrg 789a8a1cf0 Update golden verilog results 2021-05-05 15:37:27 -07:00
mrg f677c8a88d Fix predecoder offset after relocating bank offset 2021-05-05 14:44:05 -07:00