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OpenRAM
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484 Commits

Author SHA1 Message Date
mguthaus fbc2d772be Fix index order of golden tests. 2018-02-21 19:37:10 -08:00
Matt Guthaus b31f3c18af Change BSIM3 models to version 3.3.0. Add comment about multithreading selection. 2018-02-21 17:50:12 -08:00
mguthaus a22badeeb5 Fix pruned results 2018-02-21 17:48:46 -08:00
Matt Guthaus cf5f1e94b9 Update hspice results 2018-02-21 16:12:20 -08:00
Matt Guthaus 4e414b6c15 Fix unintended unmerge of changes. Bad bad. 2018-02-21 16:03:49 -08:00
Matt Guthaus a44346110b Fix merge of results. 2018-02-21 15:47:07 -08:00
Matt Guthaus fcacd46866 UPdate tests with new delay and slew names and leakage power. 2018-02-21 15:45:49 -08:00
mguthaus b8b2375346 Updated golden tests with new leakage aware power numbers. 2018-02-21 15:44:52 -08:00
Matt Guthaus 4b9ea66a42 Change names of variables to indicate transistions for clarity. 2018-02-21 15:13:46 -08:00
Matt Guthaus 71831e7737 Get delays only for successful run. 2018-02-21 14:05:39 -08:00
Matt Guthaus 9600dae7df Remove print statements. 2018-02-21 13:45:14 -08:00
Matt Guthaus 7d2f4386e2 Include leakage of non-trimmed array. Back out leakage of trimmed, add back leakage of nontrimmed. Reorgs simulation of delay and power a bit. 2018-02-21 13:38:43 -08:00
Hunter Nichols 179a27b0e3 Added some power functions. 2018-02-20 18:22:23 -08:00
Michael Timothy Grimes 4ea2a70a1b removing unnecessary unit test for pbitcell 2018-02-19 10:58:08 -08:00
mguthaus 5e8dff1e90 Fix unit tests with newest RBL delays. Fix tech problem with new spice models. 2018-02-16 13:54:05 -08:00
mguthaus c1c1ba38a3 Fix unit test to have fanout. 2018-02-16 11:53:38 -08:00
mguthaus 28fe49d069 Change RBL to allow stages and FO for configuration 2018-02-16 11:51:01 -08:00
mguthaus 1297cb4e40 Convert dff to VTG transistors in 45nm. Correct pin order in dff library cell. 2018-02-16 10:40:05 -08:00
mguthaus cb449a1cd2 Ignore non-rectangular pins. 2018-02-16 10:24:57 -08:00
Matt Guthaus 2e3e95efda Change ratio of delay line and RBL size. Need to tune it better automatically. 2018-02-14 16:50:08 -08:00
Matt Guthaus 9559421ca8 Connect dff array clk in rows and columns. 2018-02-14 16:46:26 -08:00
Matt Guthaus 2d87dcda46 dff array done except for clock net 2018-02-14 16:03:29 -08:00
Hunter Nichols 8ea384a761 Fixed merging issues with power branch 2018-02-14 15:21:42 -08:00
Matt Guthaus 0804a1eceb Add new DFF. Create DFF module. Start dff_array, not tested. 2018-02-14 15:16:28 -08:00
mguthaus 767990ca3b Update golden lib tests. Add new generic SCMOS models. Fix tech error with new msflop_in_cap name. 2018-02-13 15:54:50 -08:00
Matt Guthaus f457091bba Fix typo in precharge. 2018-02-12 15:34:01 -08:00
Matt Guthaus e32b0b8f7a Change precharge input from clk to en 2018-02-12 15:32:47 -08:00
mguthaus e210d3d49a Make some common lib memory sizes. Update Makefile to auto build and char them all. 2018-02-12 12:00:59 -08:00
mguthaus 636099c5e1 Example config only characterizes a single corner. Remove default name of sram to generate more meaningful name. Begin pre-computed IP library. 2018-02-12 11:22:47 -08:00
Matt Guthaus a12ebeed9f Add multiple process corners. Unit tests use nominal corner only. Add fake SCMOS nominal models, but they are broken. 2018-02-12 09:33:23 -08:00
mguthaus 1795dc5677 Fix three unit tests to work with new lib corner files. 2018-02-11 20:43:41 -08:00
Michael Timothy Grimes 72fc92ad95 Merge branch 'master' of https://github.com/mguthaus/OpenRAM into multiport 2018-02-11 16:47:53 -08:00
mguthaus f690532563 Add new corner-based lib files to unit tests. 2018-02-11 16:35:10 -08:00
Matt Guthaus 4dd075c7b7 Add V and C to names of lib files. 2018-02-11 16:34:32 -08:00
Matt Guthaus ce164fb7a8 Merge branch 'dev' of https://github.com/mguthaus/OpenRAM into dev 2018-02-10 10:03:26 -08:00
Matt Guthaus b75eef3684 Fix syntax error. 2018-02-10 08:02:59 -08:00
Matt Guthaus 4d35972553 Get default corner options from tech file 2018-02-09 15:49:55 -08:00
Matt Guthaus f86985821a Begin modifications for corner-based characterization. Made stimuli.py a class. Golden output files are not updated. 2018-02-09 15:33:03 -08:00
Matt Guthaus d19867e64c Move utils to base. 2018-02-09 10:42:23 -08:00
Matt Guthaus 84c798d9e4 Move last few modules to base dir 2018-02-09 10:29:37 -08:00
Matt Guthaus 7c83ef3f04 Fix missing subdir name. Comment about organization. 2018-02-09 10:27:43 -08:00
Matt Guthaus 15747b4759 Merge branch 'dev' of github.com:mguthaus/OpenRAM into dev 2018-02-09 10:25:28 -08:00
Matt Guthaus 7100d6f904 Organize top-level files into subdirs. 2018-02-09 10:25:24 -08:00
Matt Guthaus 489faaba99 Merge branch 'dev' of https://github.com/mguthaus/OpenRAM into dev 2018-02-09 10:20:56 -08:00
Matt Guthaus 13fd87d99e Accidentally committed to master. Merge branch 'master' into dev 2018-02-09 10:19:22 -08:00
Matt Guthaus d62da44329 Fix bug where path does not obey specified width. 2018-02-09 10:03:09 -08:00
mguthaus 5aa92a6549 Reorganize top-level functions a bit more. Add help info to banner. 2018-02-09 09:53:28 -08:00
mguthaus 8719a19377 Move parameter setting to config reading rather than status function. 2018-02-09 09:26:13 -08:00
Matt Guthaus 3c86f94549 Change argument name for lib in tests as well. 2018-02-08 15:28:49 -08:00
Matt Guthaus d684189241 Don't output text in SRAM during unit test. 2018-02-08 14:58:55 -08:00
Michael Timothy Grimes ce83b67350 Merge branch 'master' of https://github.com/mguthaus/OpenRAM into multiport 2018-02-08 14:27:53 -08:00
Michael Timothy Grimes b90f5c9a59 pbitcell is now a multiport cell with a read transistor that connects to RBL and RROW and a read access transistor that connects to Q and gnd 
current commit works without drc errors on freepdk45 but has drc rules not included in scn3me_subm. Does have lvs errors
adding several unit tests: the basic one that tests the full functionality of the pbitcell, one with no write ports, and one with no read ports
 2018-02-08 14:21:15 -08:00
Matt Guthaus 17716191c1 Clean up time statements in openram output 2018-02-08 13:11:18 -08:00
Matt Guthaus 6c89f7965d Refactor openram.py. 2018-02-08 12:47:19 -08:00
Matt Guthaus 54c21f6282 Added method=gear back to ngspice simulation to fix convergence bug. 2018-02-07 21:07:11 -08:00
mguthaus e8f658d356 Add updated non-pruned unit test results. 2018-02-07 19:35:21 -08:00
mguthaus 63ce754c72 Update unit test results 2018-02-07 18:48:22 -08:00
Matt Guthaus 1b4be741df Fix broken print statements 2018-02-07 17:39:42 -08:00
Matt Guthaus 9cc46453a2 Fix PWL bug to output last value. Fix bug in setup/hold use of improved PWL function. 2018-02-07 15:43:09 -08:00
Matt Guthaus 2413304f4e Update replica bitline test for new parameters. Add small test and a larger test. 2018-02-07 15:15:19 -08:00
Matt Guthaus 1a491f3cd0 Make temp directory unique for test 30. Update LEF files after delay chain size change. 2018-02-07 15:05:21 -08:00
Matt Guthaus e93517529c Make delay chain length and bitcell load parameters to enable tuning. Rename the parameters to be more descriptive. 2018-02-07 14:54:59 -08:00
Matt Guthaus 8e91552701 Remvoe newline. 2018-02-07 14:33:29 -08:00
Matt Guthaus 5dacafc698 Disable gear integration in ngspice. Not sure it is necessary anymore and it is quite slow. 2018-02-07 14:20:15 -08:00
Matt Guthaus a2bf66b063 Add metal1 gnd line to prevent DRC errors when sizing delay chain. 2018-02-07 14:15:13 -08:00
Matt Guthaus 3e4ef36efe Clean up Python comments and improve comments in stimulus file. 2018-02-07 14:04:18 -08:00
Matt Guthaus 3820861ce8 Increase control delay line from 4 inverters to 3 FO4 delays. Need to dynamically adjust this. 2018-02-07 13:10:45 -08:00
Matt Guthaus 5c4999d4cc Move delay-specific stimulus commands to delay.py. Keep stimuli.py generic. 2018-02-07 12:58:47 -08:00
Matt Guthaus 8e91faaccb Remove version from OpenRAM. We will go bit git hashes. 2018-02-06 10:56:26 -08:00
mguthaus 3af1bbba26 Updated delay tests with new delays including ps, pd, as, ad. 2018-02-06 07:58:25 -08:00
mguthaus c3592b3d46 Added new timing tests with ps,pd,as,ad caps included. 2018-02-06 05:26:27 -08:00
Matt Guthaus 33b04bbca5 Add area/perimeter of source/drain to transistor netlist. Gets rid of some spice warnings, gives better non-annotated measurements. 2018-02-05 16:02:57 -08:00
Matt Guthaus 941094ce31 Return slews to 10-90 and 90-10 so I don't have to re-hardcode the results in unit tests. 2018-02-05 15:21:53 -08:00
Matt Guthaus 4505c0f74e Improve error to setup model dir path. Use it to override FreePDK45 too. 2018-02-05 15:12:12 -08:00
Matt Guthaus 85f4438280 Exit with error if model files are not found. 2018-02-05 15:09:21 -08:00
mguthaus e01d5b7c61 Disable virtual connects at top level LVS with Calibre. 2018-02-05 14:52:51 -08:00
Matt Guthaus e2e5f45cec Correct vague comments about char cycles. End simulation after last period even though a transition would mean a failed simulation. 2018-02-05 14:07:12 -08:00
Matt Guthaus a8e1abdce8 Use method=gear for ngspice to improve convergence. Split TD for trig and targ in measure statements. Start waiting for clk neg edge trigger at clk pos edge. 2018-02-05 11:36:46 -08:00
Matt Guthaus 92095e52f7 Update new LEF files for unit tests. 2018-02-05 10:27:56 -08:00
Matt Guthaus f21ff38cae Simplify via offsets in replica bitline. Route clk_bar in control over supply rail until we get channel router working. 2018-02-05 10:22:38 -08:00
Matt Guthaus 84b42b0170 Fix bug in trim netlist. Add info comments to spice netlist and trimmed netlist. Increase verbosity for simulations. 2018-02-02 19:33:07 -08:00
Matt Guthaus 7127895270 Update LEF files for unit tests 2018-02-02 15:51:29 -08:00
Matt Guthaus d6d96907ef Route to the right in the bank decode for DRC. 2018-02-02 15:50:45 -08:00
Matt Guthaus 1415d139a3 Specify file format for sp spice extension. 2018-02-02 15:33:35 -08:00
Matt Guthaus 3873f72a58 Ensure wells are spaced in the bank select and column decoder 2018-02-02 15:26:15 -08:00
Matt Guthaus ffcf58100e Clean up column mux by moving pins to own function. Adjust spacing between column mux and bitcell to prevent DRCs. Fix up find lowest/highest functions when no objects or instances in a module. 2018-02-02 15:17:21 -08:00
Matt Guthaus 9d043b904e Remove unnecessary design reset 2018-02-02 14:26:53 -08:00
Matt Guthaus 27dbb95c19 Fix name of column mux. 2018-02-02 14:26:39 -08:00
Matt Guthaus 9d7dc4c552 Reset even if not purging temp files. 2018-02-02 14:26:09 -08:00
Matt Guthaus 2a8199c3ca Force re-extract of cells in DRC/LVS. 2018-02-02 14:21:31 -08:00
Matt Guthaus fb90b8f5fe Fix pin nameon sense amp spice. Fix NAND2 bug in hierarchical decoder. 2018-02-02 14:08:56 -08:00
Matt Guthaus 3be59fb762 Change DRC output for magic to drc.summary just like calibre output. 2018-02-02 14:07:15 -08:00
Matt Guthaus 63392c8d71 Fix gnd connection in control logic. 2018-02-02 13:04:38 -08:00
Matt Guthaus 072c8e3174 Change LVS report file to same name as Calibre 2018-02-02 12:47:42 -08:00
Hunter Nichols db4913dd9c Added skeleton code for analytical power in functions with analytical delay. 2018-02-02 12:31:34 -08:00
Matt Guthaus 74064fc854 Replace LEF files with new changes. 2018-02-02 12:31:34 -08:00
Matt Guthaus e8d001a3f9 Change wen to en in spice lib files. Check lvs report insted of stdout with netgen. 2018-02-02 12:31:33 -08:00
Matt Guthaus e4295ea61b Fix pin names to lower case. Fix write driver DRC errors and LVS error. 2018-02-02 12:31:33 -08:00
Matt Guthaus 3e2d4d631d Do not require hspice during tests. Check if a valid simulator is found, however. 2018-02-02 12:31:33 -08:00
Matt Guthaus 7c9c16e29c Fix assertion error syntax problem. Do not require hspice for functional test. Improve delay fail error message. 2018-02-02 12:31:33 -08:00
Matt Guthaus cc987daeb9 Add well around column muxes. 2018-02-02 12:31:33 -08:00
mguthaus 2ad52205c5 Clean up messages. 2018-02-02 12:31:33 -08:00
mguthaus d0c9382d97 Modify unit tests to distinguish between FAIL and ERROR. Move comparison utilities into our derived unit test class. 2018-02-02 12:31:33 -08:00
Hunter Nichols 56f7caf59f Added first test power model to sram 2018-02-02 12:31:33 -08:00
Matt Guthaus 5527e73db0 Add descriptive exceptions along with cleanup in unit test checking. 2018-02-02 12:31:33 -08:00
Matt Guthaus be1c59f10c Make both gnd rails in 6T cell from top to bottom in SCMOS. Connect in bitcell array. 2018-02-02 12:31:33 -08:00
Matt Guthaus ea5eda91fc Connect all gnd rails of RBL. 2018-02-02 12:27:24 -08:00
Matt Guthaus d552d88f45 Add -d option to not delete temp directory on successful runs. 2018-02-01 11:53:02 -08:00
Matt Guthaus 8ef1e0af2c Replace LEF files with new changes. 2018-02-01 05:43:37 -08:00
Matt Guthaus 64546ad3dd Change wen to en in spice lib files. Check lvs report insted of stdout with netgen. 2018-02-01 05:38:48 -08:00
Matt Guthaus 512448f9e8 Fix pin names to lower case. Fix write driver DRC errors and LVS error. 2018-01-31 17:37:16 -08:00
Matt Guthaus 9fea4a1a2d Do not require hspice during tests. Check if a valid simulator is found, however. 2018-01-31 16:21:43 -08:00
Matt Guthaus 590f6e01d1 Fix assertion error syntax problem. Do not require hspice for functional test. Improve delay fail error message. 2018-01-31 15:38:02 -08:00
Matt Guthaus acf3fe8376 Add well around column muxes. 2018-01-31 14:31:50 -08:00
mguthaus 4273a3717d Clean up messages. 2018-01-31 11:54:20 -08:00
mguthaus 4aee700331 Modify unit tests to distinguish between FAIL and ERROR. Move comparison utilities into our derived unit test class. 2018-01-31 11:48:41 -08:00
Matt Guthaus 1175f515c8 Add descriptive exceptions along with cleanup in unit test checking. 2018-01-31 10:35:51 -08:00
Matt Guthaus 58da8af619 Make both gnd rails in 6T cell from top to bottom in SCMOS. Connect in bitcell array. 2018-01-31 10:04:28 -08:00
Matt Guthaus 012c3923be Create empty setup.tcl file as workaround for resetting netgen LVS options until Tim fix's bug. 2018-01-31 08:28:53 -08:00
Matt Guthaus 264d55b16c Remove temp files 2018-01-30 08:05:50 -08:00
Matt Guthaus 8fcb551953 Only perform DRC not LVS on transistors 2018-01-30 08:03:54 -08:00
Matt Guthaus 1d9274621a Only remove files when cleaning temp dir 2018-01-30 07:58:31 -08:00
Matt Guthaus 0b6eddef43 Force write the specific cell during DRC. 2018-01-29 17:00:20 -08:00
Matt Guthaus 56770f558f Consolidate checking into our own unit test class. Remove all files in temp dir after each test, not just spice and gds. 2018-01-29 16:59:29 -08:00
Matt Guthaus 313e06d2af Fix pwell contact in column mux to have layers for Magic. 2018-01-29 15:53:22 -08:00
Matt Guthaus 6080b59058 Fix nand input ordering to correct netgen LVS error of wordline driver. 2018-01-29 15:36:37 -08:00
Matt Guthaus a56fa0e787 Fix wrong pin order on pnand2 LVS problem. 2018-01-29 15:31:14 -08:00
Matt Guthaus 79715ae1a2 Fix input discrepencies in pre3x8 2018-01-29 15:25:41 -08:00
Matt Guthaus 3c5ecb963d Remove level of indirection to ptx devices to allow LVS symmetries. 2018-01-29 15:25:15 -08:00
Matt Guthaus 586d80623e Remove level of indirection to ptx devices to allow LVS symmetries. 2018-01-29 15:25:00 -08:00
Michael Timothy Grimes fb2572bd71 Merge branch 'master' of https://github.com/mguthaus/OpenRAM into multiport 2018-01-28 21:44:22 -08:00
Matt Guthaus 31c192c2e9 Fix precharge nwell contact spacing DRC violatin. 2018-01-26 13:53:45 -08:00
Matt Guthaus e46a4fb115 Use any spice for the functional tests. 2018-01-26 13:53:11 -08:00
Matt Guthaus 028146f3c2 Add output explaining error for not finding simulator in unit tests. 2018-01-26 13:23:11 -08:00
Matt Guthaus 369aa85cd2 Fail simulation tests if correct spice is not found. Correctly load spice characterizer. 2018-01-26 13:00:25 -08:00
Matt Guthaus 50107636a0 Fail test early if spice simulator is not found. 2018-01-26 12:47:32 -08:00
Matt Guthaus 1dc7752429 Fix 6T and replica cell contact spacing issues with Magic DRC. 
DRC/LVS passing for all parameterized gates.
Magic and GDS match for SCMOS rules again.
 2018-01-26 12:39:00 -08:00
Matt Guthaus ac8eada0d8 Fix devices sizes in SCMOS sense amp. Elaborate magic/netgen scripts in comments. 2018-01-24 13:02:55 -08:00
Matt Guthaus 1b2df3a5a1 Properly ignore ad as, pd, ps property errors 2018-01-22 17:50:53 -08:00
Matt Guthaus 2468f224d9 SCMOS library cells passing LVS (with property errors though). Permute must be enabled before compare, duh. 2018-01-22 17:14:39 -08:00
Matt Guthaus fb2ed1d46c Add wells to fix DRC errors in SCMOS library cells. 2018-01-22 16:28:20 -08:00
Matt Guthaus f572b83671 Add Makefile for parallel test execution. 2018-01-22 13:39:07 -08:00
Matt Guthaus 10ced33127 Fixed command line arguments to take priority over config file. Any option can be specified in config file now. 2018-01-21 11:21:09 -08:00
Matt Guthaus 84ec7a5be0 Convert unit tests to use new options as well. 2018-01-19 17:23:38 -08:00
Matt Guthaus 95fab1ca71 Remove personalized temp dir. 2018-01-19 16:39:14 -08:00
Matt Guthaus 490a70dee9 Simplify configuration file to allow all options to be over-riden. Move default module types to options.py to simplify config file. 2018-01-19 16:38:19 -08:00
Matt Guthaus 72b0617e81 Merge branch 'dev' of github.com:mguthaus/OpenRAM into dev 2018-01-19 16:19:12 -08:00
Matt Guthaus efa465757c Remove dead code ptx_port. 2018-01-19 16:19:05 -08:00
Matt Guthaus fcc533ec11 Initial LVS using netgen. pinv nad pnand2 pass. No property checks in LVS yet. 2018-01-17 16:48:35 -08:00
Matt Guthaus ba489f0291 Only check if using magic with freepdk when LVSDRC is enabled. 2018-01-17 07:38:29 -08:00