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1083 Commits

Author SHA1 Message Date
mrg f1f4453d14 Add column decoder module with power supply straps. 2022-05-17 13:32:19 -07:00
mrg b1bb9151c4 Reimplement off grid pins. 
Long pins aren't accessed on end pins anymore.
Fix problem with multiple non-enclosed space causing blockages.
Add partial pin offgrid enclosure algorithm.
 2022-05-02 15:43:14 -07:00
mrg 64f2f90664 Rework replica_bitcell_array supplies 
Uses layer and direction preferences in tech file.
Places straps on left/right or top/bottom.
 2022-04-19 08:50:11 -07:00
mrg 23b5655cab Split replica_bitcell_array test 2022-03-23 15:59:29 -07:00
mrg 9f7426052d Split port_address tests 2022-03-23 14:46:41 -07:00
mrg e31bec131c Remove 1rw1r combined test and add separate tests. 2022-03-22 11:59:04 -07:00
mrg 229a3b5b3d By default uniquify instances based on macro name. 2022-03-11 18:01:45 -08:00
mrg 4567c2ebcd Add space after docker command. Regress to klayout v0.27.4 2022-03-10 08:37:48 -08:00
mrg e16defdae4 Add a sleep to see if problem is async one 2022-03-09 10:24:50 -08:00
mrg f17d661e3a Add spare column option to tests for sky130 2022-03-07 07:58:41 -08:00
mrg 4faf97005f Add even columns for sky130 to ring test 2022-03-06 12:21:09 -08:00
mrg 6eeb81b9fe Skip sky130 23_lib tests and 4096 row hierarchical decoder test 2022-03-06 11:27:13 -08:00
mrg a0f1327f5e Add odd rows to 23_lib tests 2022-03-06 11:26:18 -08:00
mrg 6da3e44b6f Split up 06_hierarchical_decoder test 2022-03-06 11:26:03 -08:00
mrg 8c911f70b9 Build changes. 
Don't pull docker since it will be build by CI.
Shuffle tests to stagger technologies and test types.
 2022-03-06 10:31:43 -08:00
mrg 4fac069c3c Skip hspice tests in docker 2022-03-01 14:44:04 -08:00
mrg c12c006799 Add verbose option 2022-03-01 10:50:49 -08:00
mrg 38494458e3 Fix incorrect port 1w to 1r 2022-03-01 10:44:56 -08:00
mrg c223c1ad1c Run docker pull before running all tests for regression 2022-03-01 10:33:40 -08:00
mrg 184888b370 Skip 16 way test for now 2022-02-28 12:03:01 -08:00
mrg 27b4d2edb1 Add 16 way mux SRAM tests 2022-02-28 11:53:24 -08:00
mrg 82c2bc329f Split bank and col mux tests. 2022-02-23 15:39:32 -08:00
mrg 6389d4ac82 Skip all func tests 2022-02-23 15:31:15 -08:00
mrg 1742927751 Split port data tests into individual tests 2022-02-23 11:12:32 -08:00
mrg a75d9fcc76 Fix failing test output of Makefile 2022-02-11 13:11:24 -08:00
mrg a35ab45843 Conditionally set TEST_TECHS. Skip pand4 for sky130. 2022-02-10 11:30:20 -08:00
mrg c471823626 Run individual tests on all technologies by default 2022-02-10 11:18:52 -08:00
mrg 51097b2c8b Revert rm in makefile 2022-02-02 09:38:27 -08:00
mrg 39f1199b63 Always delete result subdir to prevent bad and ok simultaneously 2022-02-02 09:36:19 -08:00
mrg 2d2620d21a Remove dir from bad tests 2022-02-02 07:11:13 -08:00
mrg c75968401c Update for detailed skips. Added some sky130 skips. 2022-02-08 16:04:43 -08:00
mrg 16238af584 Print failing tests before exit 2022-02-08 13:07:37 -08:00
mrg 4d62cbd345 Move pdk paths to docker invocation 2022-02-08 12:05:39 -08:00
mrg b1e1763e14 Fix PDK path for freepdk45 and list FAILED tests explicitly at end. 2022-02-08 11:35:29 -08:00
mrg b641bc8eef Check proper subdir for bad files 2022-02-07 16:30:18 -08:00
mrg a3d3aa514b Add target for all technologies 2022-02-07 11:27:10 -08:00
mrg ee97d87bdf Fix total regress pass or fail check. 2022-02-06 12:36:22 -08:00
mrg 89688de3cf Remove outside of docker space 2022-02-06 09:48:30 -08:00
mrg 93c6565b66 Add total failure of tests 2022-02-06 09:13:36 -08:00
mrg 8653b88206 Remove working temp directories 2022-02-06 09:06:20 -08:00
mrg d716a1c361 Don't stop on fail, archive all results, create .bad file on fail. 2022-02-05 07:50:06 -08:00
mrg e45e2f77c9 Rework regression to use docker. 2022-02-04 17:43:48 -08:00
mrg 049751ae1f FreePDK45 running with klayout and Sky130 running with magic. 2022-02-03 10:19:28 -08:00
mrg 63a6168b35 Merge branch 'dev' into klayout 2022-02-01 11:57:56 -08:00
mrg 06d391b3e3 Keep files during runs in Makefile 2022-01-13 14:41:24 -08:00
mrg 34dd46c918 Exceptions for sky130 spare columns tests 2021-12-17 10:30:43 -08:00
mrg 4fa084f272 Add 1rw decoder test 2021-12-17 10:18:20 -08:00
mrg edf3a701e4 Update options for arguments and readme. 2021-11-16 14:33:35 -08:00
mrg c102ed728c Move tests to test Makefile 2021-11-03 11:36:19 -07:00
mrg e6a009312e Move mem reg before usage for compatibility 2021-10-13 09:46:02 -07:00
mrg 178f1197ca Use spare rows only for sky130 2021-09-07 16:49:11 -07:00
mrg 83f2d14646 Fix unit test errors. 
Skip test 50s for now.
Change golden power values in xyce delay test.
 2021-09-07 14:07:22 -07:00
mrg b2389fe00f Change tolerance to 30% 2021-09-03 14:04:39 -07:00
mrg 90a4ad4d75 Update size of 30 config tests to 2 bits. 2021-07-28 12:05:31 -07:00
mrg 0464ec3f16 Skip 50 tests 2021-07-01 16:38:39 -07:00
mrg 55f09d00a4 Make replica_column sky130 friendly 2021-07-01 16:15:13 -07:00
mrg 879f945aa7 Add risc5 functional tests 2021-07-01 16:13:14 -07:00
mrg 6be24d4c6c Only 25 cycles 2021-07-01 12:50:20 -07:00
mrg 3d2b192682 Add conditional spare row/col to a couple unit tests 2021-07-01 12:49:30 -07:00
mrg 927de3a240 Debugging then disabling spare cols functional sim for now. 2021-06-29 15:47:53 -07:00
mrg c4aec6af8c Functional fixes. 
Off by one error of max address with redundant rows.
Select reads 3x more during functional sim.
 2021-06-29 09:33:44 -07:00
Hunter Nichols 294ccf602e Merged with dev, addressed conflict in port data 2021-06-21 17:23:32 -07:00
mrg 67877175b2 Fix error in no spare column verilog 2021-06-18 08:41:26 -07:00
Jesse Cirimelli-Low 7b7c72706a merge in dev 2021-06-17 09:49:32 -07:00
Jesse Cirimelli-Low 1ce6b4d41a fix freepdk45 2021-06-17 03:21:01 -07:00
Hunter Nichols 131ff8bcef Changed the regression test to only run models for the output being tested. 2021-06-16 23:50:20 -07:00
mrg afe0902547 Enable small short func tests 2021-06-16 19:13:50 -07:00
Hunter Nichols 4132decd32 Merge branch 'dev' into automated_analytical_model 2021-06-14 14:45:48 -07:00
Hunter Nichols 4d22201055 Changed name of regression test since we currently only test the delay. 2021-06-14 10:57:20 -07:00
mrg 53107a8322 Add ring test 2021-06-13 15:03:41 -07:00
Jesse Cirimelli-Low 73cc6b3891 uncomment 4x16 decoder 2021-06-11 18:20:36 -07:00
Hunter Nichols 4ec2e1240f Merge branch 'dev' into automated_analytical_model 2021-06-09 15:45:41 -07:00
Hunter Nichols ccf98ad5a6 Added accuracy check in regression model test. 2021-06-09 13:44:42 -07:00
mrg a1cb20878d Swap LH/HL hold times in sky130. 2021-06-08 11:14:27 -07:00
Hunter Nichols 331e6f8dd5 Added functions for testing accuracy of current regression model and associated test. 2021-06-04 15:04:52 -07:00
Hunter Nichols da67edbde8 Changed input format for delay module in xyce delay test. 2021-05-26 20:11:30 -07:00
Hunter Nichols 2f4f8ca912 Fixed conflicts in delay and elmore modules on merge with dev. 2021-05-25 15:25:43 -07:00
Hunter Nichols 23368c0fcf Updated tests and elmore model with load_slew lists. Changed naming on characterization output to not clash with testing. 2021-05-25 14:49:28 -07:00
mrg d51ec4fe45 Add Xyce tests 2021-05-21 12:04:26 -07:00
mrg d43edd95e4 Update golden tests for verilog 2021-05-06 19:56:22 -07:00
mrg 789a8a1cf0 Update golden verilog results 2021-05-05 15:37:27 -07:00
mrg 5b556e6ef5 Update unit test results with new Verilog models. 2021-04-15 15:48:20 -07:00
mrg b510925bdb Enable pruning by default (except on unit tests) 2021-04-07 16:08:29 -07:00
mrg d609e4ea04 Reimplement trim options (except on unit tests). 
Allow trim netlist to be used for delay and functional simulation.
Each class implements a "trim_insts" set of instances that can be removed.
By default far left, right, top and bottom cells in the bitcell arrays are kept.

Use lvs option in sp_write

Fix lvs option in sram.
 2021-04-07 16:07:56 -07:00
mrg b9086dbbe5 Add unit test times to output. 2021-03-26 06:56:58 -07:00
mrg 4a40e96f6d Control logic route changes. 
Move wl_en to top control signal.
Route wl_en directly to port_address.
Reorder input bus to bank.
 2021-03-24 14:32:10 -07:00
mrg fae72ca993 Test new archive options for github actions. 2021-03-23 13:06:36 -07:00
mrg 7b270514e1 Update multithreaded regression. 
Only do 2 threads for 30 tests.
Don't archive results since they are purged anyways.
16 threads for regression.
Purge temp during regression.
 2021-03-23 10:45:56 -07:00
mrg 671470f5f2 Skywater changes. 
Default 1 thread and no temp subdirectory.
Add skywater setup/hold golden data
Add CLI option for simulation threads (-m)
Add compatibility mode option and nomodcheck for ngspice to speed up sky130 model loading.
Make subdir when using default /tmp dir.
Pass num_threads so temp subdirs are created.
 2021-03-22 15:48:14 -07:00
mrg 4ab694033d Merge remote-tracking branch 'bvhoof/dev' into dev 2021-03-01 12:16:26 -08:00
mrg 7610f23fc7 Sub temp directory. Add github archive. 2021-02-10 15:39:12 -08:00
Bob Vanhoof 3dfc039f6f add technology option passtrough in test 30 2021-02-09 09:32:35 +01:00
mrg b83d93cc9a GitHub Actions CI flow. 2021-02-08 15:46:02 -08:00
mrg e043aaffb3 Don't print DRC/LVS/PEX run stats in regress.py 2021-02-03 15:17:28 -08:00
mrg 19e99d1c7b Enable parallel regression testing. 2021-02-03 14:19:11 -08:00
Hunter Nichols df8d59f32e Merge branch 'dev' into automated_analytical_model 2021-02-01 01:49:45 -08:00
mrg bc8fd4a882 Merge branch 'supply_router' into dev 2021-01-25 11:01:48 -08:00
Matt Guthaus 30fc81a1f0 Update copyright year. 2021-01-22 11:23:28 -08:00
mrg db142bcd5a Rename pins to original names 2021-01-21 15:22:54 -08:00
Hunter Nichols cd84cf1973 Merged and addressed conflict in delay.py 2021-01-06 01:37:16 -08:00
Hunter Nichols 48baf3ab4e Updated test to use new analytical class 2021-01-06 01:34:44 -08:00
mrg 9ef4cf14c5 Check for drc/lvs aux scripts in test 30 2020-12-23 07:25:24 -08:00
mrg e59333a232 Change options to use route perimeter pins and supply as tree by default. 2020-12-23 07:25:07 -08:00
mrg ae1c889235 Updates to IO signal router. 
Route signals to perimeter using maze router.
Move IO pins without perimeter pins to M3 using add_io_pin (like add_power_pin).
 2020-12-22 09:39:58 -08:00
mrg 348001b1c8 Supply tree uses signal grid. PEP8 cleanup. 2020-12-21 13:51:50 -08:00
mrg 3a3ecb27d2 Merge branch 'dev' into supply_router 2020-12-17 15:53:31 -08:00
Hunter Nichols 56c4c89720 Adjusted error margin for period in analytical model and added check in model test. 2020-12-17 01:34:53 -08:00
mrg d5ed45dadf Make default router tree router 2020-12-16 16:42:19 -08:00
mrg fd118c62e5 Default zom is None not negative. 2020-12-15 13:27:36 -08:00
Hunter Nichols 942675051a Added test for linear regression model. 2020-12-14 14:37:53 -08:00
mrg 87493e1e30 Disable pex tests. 2020-12-11 11:47:10 -08:00
mrg 38bf12771b Make DRC/LVS scripts use relative paths 2020-12-11 10:06:00 -08:00
mrg 9717794400 Remove extra debug statement 2020-12-08 11:59:14 -08:00
mrg 0008de3e59 Change test 14 to odd sizes for use in sky130. 2020-12-08 10:32:23 -08:00
mrg e134e07522 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2020-11-20 16:57:14 -08:00
mrg f729e9fca7 Fix new replica_bitcell_array refactor with end caps. Remove single port end cap exceptions. 2020-11-20 16:56:07 -08:00
Hunter Nichols 35e1a523cc Changed named on delay chain sizing variable. Automatic sizing default is False. 2020-11-17 14:29:01 -08:00
mrg 7512aa6e70 Skip test 50 which is too slow 2020-11-16 08:59:25 -08:00
mrg 2f994b8c0a Change custom cells to use set_ports setter 2020-11-14 07:15:27 -08:00
mrg 63941a10e1 Add None as sp_file parameter to local_drc_check 2020-11-12 10:01:38 -08:00
mrg 03dad01e4c Use readspice to define ports from sp netlist in Magic extract. 2020-11-10 17:06:24 -08:00
mrg 31ae56ff39 Simplify to a single DRC/LVS library test. 2020-11-10 16:45:00 -08:00
mrg 2c203530ad Merge branch 'drclvs' into dev 2020-11-09 14:36:36 -08:00
mrg 0ba2feee53 Fix errors in new run_sim calls and corners 2020-11-09 13:59:46 -08:00
mrg 532492d5ae Output functional stimulus to output directory. 2020-11-09 12:00:25 -08:00
mrg 31d21e169f Skip LEF test as correct output keeps changing. 2020-11-09 11:14:55 -08:00
mrg 66633a843b Add PDK layer names to tech file 2020-11-09 09:10:43 -08:00
mrg 2da9c307db Disable 4x16 decoder test for now 2020-11-06 13:50:04 -08:00
mrg 147649e142 Why was single port decoder test a dual port? 2020-11-06 12:21:30 -08:00
mrg 2c76a2680f Adjust openram options. 
Remove option -d (dontpurge) and replace with keeptemp
Add option -d (debug) to drop into pdb.
Add option -k (--keeptemp) to keep temp files
 2020-11-05 13:12:26 -08:00
mrg fb0b285652 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2020-11-04 10:40:20 -08:00
mrg 6e12d4d46c Skip tri gate array test 2020-11-04 06:57:51 -08:00
mrg 29ac541b28 Refactor dynamic cell name to utilize base class 2020-11-03 13:18:46 -08:00
mrg 87419bd640 Fix bitcell and pbitcell with different cell names 2020-11-03 11:30:40 -08:00
mrg cb3e9517bb Use cell_properties to override cell names 2020-11-03 07:06:01 -08:00
mrg da721a677d Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
mrg 8c4584daa1 Missing import fix. 2020-11-03 06:09:42 -08:00
mrg f9787eb878 Use bitcell_base for all bitcells. Fix missing setup_bitcell call 2020-11-02 17:00:15 -08:00
mrg fa89b73ef8 PR from mithro + other changable GDS file names 2020-11-02 16:00:16 -08:00
mrg cbf9c48504 Names in skiptests changed. Reduce grid router verbosity. 2020-10-23 09:22:59 -07:00
mrg 43d2058b3c Remove temp files 2020-10-08 10:35:27 -07:00
mrg 9a0fc8047b Remove diff 2020-10-08 09:53:52 -07:00
mrg 7076c376e0 Remove log from branch 2020-10-08 09:53:17 -07:00
jcirimel 1e7ae06b7e fix extra wl in col end, work on bring wl pins out to row end array, TODO: mirror alternating row end 2020-10-08 05:32:03 -07:00
jcirimel d40c3588ed no wl for col end 2020-10-08 03:34:16 -07:00
jcirimel 4a1a7e637e merge in dev 2020-10-07 11:54:07 -07:00
jcirimel 888646cdf9 merge in wlbuf and begin work on 32kb memory 2020-10-06 05:03:59 -07:00
mrg a145a37cf7 PEP8 fixes in regress.py 2020-10-05 15:56:12 -07:00
mrg da83824a70 Merge branch 'wlbuffer' into dev 2020-10-05 15:33:54 -07:00
mrg c4952ca8be Skip full sram pex test too slow 2020-10-05 13:51:20 -07:00
mrg 4a58f09c1c Use 4x16 decoder with dual port bitcell in tests. 2020-10-05 10:52:56 -07:00
mrg c06b02e6fc Rename single_level_column_mux to just column_mux 2020-10-05 08:56:51 -07:00
mrg f8146e3f69 Add decoder4x16 2020-10-02 15:52:09 -07:00
mrg 64cc620440 Add sram pex test 2020-10-02 14:55:10 -07:00
mrg 1fc4040607 Add pand4 and pnand4 2020-10-02 14:54:12 -07:00
mrg a62b82128c Skip riscv func test because too slow 2020-10-02 13:33:58 -07:00
mrg 1e24b780bb Initial pex sram test. 2020-10-02 13:32:52 -07:00
mrg b32c123dab PEP8 cleanup. Un-hard-code bitcell layers. Remove dead variable. 2020-10-01 11:10:18 -07:00
Matt Guthaus 112d57d90a Enable riscv tests 2020-09-30 12:39:40 -07:00
mrg f4e6a8895b Update riscv unit test 2020-09-30 08:50:58 -07:00
jcirimel 7cbf456a4f sky130 rba done 2020-09-30 07:34:05 -07:00
mrg b147e8485c PEP8 formatting 2020-09-29 16:52:27 -07:00
mrg 8e908f016e PEP8 formatting 2020-09-29 13:43:59 -07:00
mrg 54890a8d77 Add new golden data 2020-09-29 13:43:34 -07:00
mrg 0c280e062a Fix func test with row/col of 0. PEP8 cleanup. Smaller global test case. 2020-09-29 11:35:58 -07:00
mrg 9032bb9869 Add global wordline delay test 2020-09-29 10:28:57 -07:00
mrg 1eb8798bb6 Add global functional test 2020-09-28 16:12:09 -07:00
mrg 6f06bb9dd5 Create sized RBL WL driver in port_address 2020-09-28 11:30:21 -07:00
jcirimel 3dd72cdeac progress with rba pin mismatch 2020-09-23 08:37:32 -07:00
jcirimel 17e6e5eb16 row end col done 2020-09-23 08:02:56 -07:00
jcirimel 5c263e0001 rep col done w/o power pins 2020-09-23 06:24:52 -07:00
jcirimel 7afe3ea52c replica col arrangement done 2020-09-23 04:51:09 -07:00
jcirimel efdc171b14 make split wl specific to each port 2020-09-23 00:08:34 -07:00
mrg 392afd4d4b Add unit test for hierarchical wordline. 2020-09-15 13:46:21 -07:00
jcirimel d22164bd48 single port progess 2020-09-14 18:11:38 -07:00
mrg 55dd4d0c47 Global bitcell array working 2020-09-14 14:35:52 -07:00
mrg 12fd60e8c3 Fix pbitcell array test 2020-09-09 12:02:09 -07:00
mrg 7bb21fb73f Updates to local and global arrays to make bitline and wordlines consistent. 2020-09-09 11:54:46 -07:00
jcirimel 73443c8c95 Merge branch 'dev' into s8_single_port 2020-09-01 15:37:10 -07:00
mrg c1c631abe1 Global bitcell array passes LVS/DRC 2020-09-01 10:57:49 -07:00
mrg 7bdce3ca9a Don't make dummy bitlines pins for simplicity 2020-09-01 09:55:23 -07:00
mrg 11a82b7283 Fixed local bitcell array for single and dual port 2020-08-27 14:03:05 -07:00
mrg e92337ddaf Separate get_ and get_all for bitlines and wordlines 2020-08-25 17:08:48 -07:00
mrg 28bd93bf51 Still working on array refactor 2020-08-25 11:50:44 -07:00
mrg 8dee5520e0 Standardize array names independent of bitcell 2020-08-21 13:44:35 -07:00
jcirimel 854d51c721 merge dev 2020-08-19 14:25:41 -07:00
mrg b762580ee2 Skip global test for now 2020-08-19 11:36:21 -07:00
mrg 224e359208 Fix pin order for replica array 2020-08-18 15:59:05 -07:00
mrg f58fc6579f Rename local/global tests 2020-08-18 15:58:44 -07:00
mrg e3e4bac922 Fix replica bitcell array for right only RBL 2020-08-18 15:47:52 -07:00
mrg 59d65c46c3 Fix bug in not adding RBLs in local bitcell array 2020-08-18 15:11:10 -07:00
mrg b288bba43e Add global bitcell array test 2020-08-18 14:29:23 -07:00
mrg 99e252d6d4 Update interface of RBL array 2020-08-17 17:19:07 -07:00
mrg b1e55f9072 Add local bitcell array 2020-08-17 15:14:42 -07:00
jcirimel e7c9914d77 decoder passing except for bus route 2020-08-13 16:20:39 -07:00
mrg 797c41c750 Skip local bitcell array test 2020-08-13 14:36:39 -07:00
mrg 8e890c2014 Replica bitcell with all the fixings 2020-08-11 15:00:29 -07:00
mrg eef97ff215 Reabstracting bit and word line names. 2020-08-06 11:17:49 -07:00
mrg 2fa561f98f Local bitcell array edits. Skip test by default. 2020-07-29 10:08:13 -07:00
mrg c260297366 Allow replica_bitcell_array without the replica columns for local wordlines. 2020-07-27 16:22:21 -07:00