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3302 Commits

Author SHA1 Message Date
Jesse Cirimelli-Low 25bc178132 extend input rail 2021-06-14 15:13:17 -07:00
Hunter Nichols 4132decd32 Merge branch 'dev' into automated_analytical_model 2021-06-14 14:45:48 -07:00
Hunter Nichols 74b55ea83b Added a graph exclusion clear for the mux to prevent previous graph creations causing bugs. 2021-06-14 14:39:54 -07:00
Hunter Nichols 7df36a916b Added an exclusion for unused column mux paths to prevent multiple outputs paths in graph. 2021-06-14 13:51:52 -07:00
Hunter Nichols 4d22201055 Changed name of regression test since we currently only test the delay. 2021-06-14 10:57:20 -07:00
mrg 159d0ed603 Fix s_en spacing problem. 2021-06-13 15:08:05 -07:00
mrg 53107a8322 Add ring test 2021-06-13 15:03:41 -07:00
mrg d6a72aed37 Add 2x1 perimter pins to satisfy minimum area rule. 2021-06-13 15:00:46 -07:00
mrg 2e23fffadd Fix comment 2021-06-13 14:18:55 -07:00
Jesse Cirimelli-Low 73cc6b3891 uncomment 4x16 decoder 2021-06-11 18:20:36 -07:00
Jesse Cirimelli-Low bee9b07516 fix decoder routing 2021-06-11 18:19:07 -07:00
Jesse Cirimelli-Low 2e72da0e53 rotate input to rail contacts for drc 2021-06-10 14:01:28 -07:00
Jesse Cirimelli-Low 247a388ab5 Merge branch 'dev' into laptop_checkpoint 2021-06-09 18:25:45 -07:00
Jesse Cirimelli-Low 10f561648f remove hierarchical decoder vertial m1 above pins 2021-06-09 18:24:21 -07:00
mrg 8964abc2b7 Change simulator based on one in use. 2021-06-09 16:02:32 -07:00
Hunter Nichols 4ec2e1240f Merge branch 'dev' into automated_analytical_model 2021-06-09 15:45:41 -07:00
Hunter Nichols c50ffe70b3 Added more configs for model and respective data. 2021-06-09 15:42:15 -07:00
Hunter Nichols ccf98ad5a6 Added accuracy check in regression model test. 2021-06-09 13:44:42 -07:00
Hunter Nichols b6b20c1f43 Removed level 0 debug statements for bitlines naming. 2021-06-09 12:53:31 -07:00
Hunter Nichols f25dcf1b63 Fixed issue with bitline name warning occuring when no issue is present. 2021-06-09 12:52:26 -07:00
Hunter Nichols a73bfe6c2c Added more configs for model and data from scn4m_subm run. 2021-06-09 10:35:58 -07:00
mrg a1cb20878d Swap LH/HL hold times in sky130. 2021-06-08 11:14:27 -07:00
Hunter Nichols 3d82718f5a Changed neural network model to be sklearn based 2021-06-07 12:26:45 -07:00
mrg 27c6a13923 Back out drc listall count for detecting errors 2021-06-04 15:51:50 -07:00
mrg cf61096936 Merge branch 'laptop_checkpoint' into dev 2021-06-04 15:22:37 -07:00
Hunter Nichols 331e6f8dd5 Added functions for testing accuracy of current regression model and associated test. 2021-06-04 15:04:52 -07:00
Hunter Nichols 84783bbac5 Added more configs for model generation 2021-06-04 13:38:17 -07:00
Hunter Nichols 54639bbb94 Added more data for regression models 2021-06-04 13:37:21 -07:00
mrg 6643759345 Add back drc listall with correct output. 2021-06-04 11:06:39 -07:00
mrg 53791d79c8 spacing must be two extensions (one for each cell) 2021-06-04 08:56:06 -07:00
mrg cc4c6e909b Check if s_en exists before using it 2021-06-04 07:48:26 -07:00
mrg 4107c983e2 Make sure channel route is below s_en 2021-06-04 07:14:49 -07:00
mrg 537fd6eff9 Use None instead of empty string for tool names. 2021-06-01 16:41:14 -07:00
mrg 1ded978256 Change nwell from gnd to vdd. dnwell space added. 2021-06-01 15:10:55 -07:00
Hunter Nichols 0692593236 Specified line terminator in sim_data output to prevent carriage returns 2021-06-01 14:49:08 -07:00
Hunter Nichols 35ce838c8a Fixed issues with makefile with removal of prerequisite 2021-05-31 01:07:12 -07:00
Hunter Nichols 4da9d3beaf Removed config file as a prereq in makefile due to errors. Changes in config file will not result in a re-simming of that configuration now and will require a clean. 2021-05-30 23:58:24 -07:00
Hunter Nichols ccfda16ab2 Changed makefile to include okay files to indicate which configs have already been simulated for the existing models. 2021-05-30 22:19:56 -07:00
Jesse Cirimelli-Low 24b45ca2d4 use flat magic files instead of gds flatten subcell 2021-05-29 16:54:36 -07:00
Jesse Cirimelli-Low 131ca42512 merge in dev 2021-05-29 16:11:21 -07:00
Jesse Cirimelli-Low 97f43e31f0 remove breakpoint 2021-05-29 16:08:31 -07:00
mrg e944a5ec02 Use open_pdks setup.tcl if available. Set vdd/gnd/sub in run_ext.sh 2021-05-28 16:39:48 -07:00
Jesse Cirimelli-Low 6705f99855 merge in dev 2021-05-28 14:06:23 -07:00
Jesse Cirimelli-Low 1a894a99dd push bias pins to top level power routing 2021-05-28 13:41:58 -07:00
mrg 9e8d39f911 Remove debug gds dump 2021-05-28 13:31:19 -07:00
mrg d6d0df97f8 Get rid of write_size error when write_size==word_size 2021-05-28 13:06:12 -07:00
mrg 77f221d859 Separate supply pin type from route supplies option 2021-05-28 11:55:50 -07:00
mrg 013c5932a0 Valid type is tree not single 2021-05-28 11:26:41 -07:00
mrg f6587badad Improve supply routing for ring and side pins 2021-05-28 10:58:30 -07:00
Hunter Nichols da67edbde8 Changed input format for delay module in xyce delay test. 2021-05-26 20:11:30 -07:00
Hunter Nichols b3bcf48d2e Merge branch 'dev' into automated_analytical_model 2021-05-26 18:42:24 -07:00
Hunter Nichols a53c6c51ed Added sim data for freepdk45 and removed stale data 2021-05-26 18:40:46 -07:00
mrg 61221ff4fa Allow tree type 2021-05-26 17:46:41 -07:00
mrg 8bf37ca708 Connect dnwell taps to gnd 2021-05-26 17:38:09 -07:00
mrg 2b5013fd69 Config example changes 2021-05-26 16:14:48 -07:00
mrg 7736d3b927 Fix updated side pin option 2021-05-26 16:14:46 -07:00
mrg 6de5787e58 Fix offsets for ring 2021-05-26 16:14:16 -07:00
mrg e611f66767 Add dnwell 2021-05-26 16:14:16 -07:00
mrg 6493d1a7f4 Add dnwell 2021-05-26 16:14:16 -07:00
mrg cc91cdf008 Add power ring pin 2021-05-26 16:14:14 -07:00
mrg bc793ec3d8 PEP8 2021-05-26 16:13:47 -07:00
mrg 8610144ccb Fix write size warning 2021-05-26 16:13:47 -07:00
mrg e16f44cc81 Update lib file with external supply names 2021-05-26 15:34:32 -07:00
mrg d579a60382 Fix external supply names in verilog 2021-05-26 15:26:20 -07:00
mrg 7fa6c7ce0f Typo in wmask supply variable 2021-05-26 15:24:31 -07:00
mrg 4a8e0cdabb Add top-level pin functionality 2021-05-26 15:04:52 -07:00
Hunter Nichols 2f4f8ca912 Fixed conflicts in delay and elmore modules on merge with dev. 2021-05-25 15:25:43 -07:00
Hunter Nichols 52bf8d09d7 Added tech dir to model output so different tech dont overwrite the outputs of eachother. 2021-05-25 15:21:32 -07:00
Hunter Nichols 76f5578cc1 Removed path delays from characterization output to not disturb the current testing flow. 2021-05-25 15:19:27 -07:00
Hunter Nichols 23368c0fcf Updated tests and elmore model with load_slew lists. Changed naming on characterization output to not clash with testing. 2021-05-25 14:49:28 -07:00
Hunter Nichols 1488b31dce Adjusted model prediction to account for a single datafile. Adjusted unscaling data as well. 2021-05-24 12:53:51 -07:00
Hunter Nichols 53503f40d2 Changed util functions to expect multiple outputs in data. Changed train models to account for multiple outputs when reading in data. 2021-05-24 12:03:26 -07:00
Hunter Nichols a4cb539f72 Removed old sim data csvs and added a new version. Added a default check for LAS in data extraction. 2021-05-24 10:44:46 -07:00
Jesse Cirimelli-Low f9eae3fb80 route bias pisn 2021-05-24 02:42:04 -07:00
mrg 9c01e22281 Prioritize Xyce. 2021-05-21 12:05:10 -07:00
mrg f856a44376 Restrict to direct KLU solver 2021-05-21 12:04:26 -07:00
mrg fc17a1ff45 Xyce can be capital or lower case 2021-05-21 12:04:26 -07:00
mrg d51ec4fe45 Add Xyce tests 2021-05-21 12:04:26 -07:00
mrg eadf7eedc5 Prioritize Xyce to last until bugs resolved. 2021-05-21 10:01:37 -07:00
Hunter Nichols 4e40017fdc Added model configs adapted from OpenRAM Library 2021-05-20 15:26:24 -07:00
Hunter Nichols 41c8eeb23c Adjusted paths in makefile for generating data used in regression models 2021-05-20 13:05:16 -07:00
Hunter Nichols 269b698b0a Fixed issues with csv generation. Added regex parsing to determine corners from datasheet. 2021-05-18 23:41:16 -07:00
mrg 7c001732b1 Add destination file as dot file 2021-05-18 14:54:13 -07:00
mrg 191b382171 Change magic to use OPENRAM_MAGICRC if defined. 2021-05-18 13:27:11 -07:00
Hunter Nichols 36b1bc1284 Added script to extract data from datasheet output and store in CSV. 2021-05-17 14:04:20 -07:00
Hunter Nichols 0434e57609 Added target in makefile to run configs and store results in tech directory. 2021-05-17 14:03:32 -07:00
mrg 3abebe4068 Add hierarchical seperator option to work with Xyce measurements. 2021-05-14 16:16:25 -07:00
mrg 7534610cdd Add MPI capability for Xyce threading. 2021-05-14 11:45:37 -07:00
mrg 507ad9f33d Change sim threads to 3. 2021-05-14 11:45:10 -07:00
mrg 67a67111a6 Initial Xyce support. 2021-05-14 11:28:29 -07:00
mrg 3959cf73d1 Remove setup/hold measure and compute it directly. 2021-05-14 10:11:14 -07:00
mrg 9555b52aaa Remove setup/hold measure and compute it directly. 2021-05-14 10:01:10 -07:00
Jesse Cirimelli-Low 0ba229afe5 Merge branch 'dev' into laptop_checkpoint 2021-05-07 19:06:17 -07:00
Jesse Cirimelli-Low e5662180e8 single port 20 series tests running 2021-05-07 18:44:45 -07:00
Jesse Cirimelli-Low 6d8411d19f use consistent amp spacing 2021-05-07 11:29:43 -07:00
mrg d43edd95e4 Update golden tests for verilog 2021-05-06 19:56:22 -07:00
mrg 57c58ce4a5 Always route data dff on m3 stack. 2021-05-06 17:14:39 -07:00
mrg 453f260ca2 Add commented save npz file for intern 2021-05-06 17:14:27 -07:00
mrg e995e61ea4 Fix Verilog module typo. Adjust RBL route. 2021-05-06 14:32:47 -07:00
mrg c057490923 Delay chain should have same height cells as control logic to align supplies. 2021-05-05 15:45:28 -07:00
mrg 789a8a1cf0 Update golden verilog results 2021-05-05 15:37:27 -07:00
mrg f677c8a88d Fix predecoder offset after relocating bank offset 2021-05-05 14:44:05 -07:00
mrg 120c4de5ad Fix placement of delay chain to align with control logic rows. 2021-05-05 14:21:53 -07:00
mrg b3948121df Default supply routing is tree. 2021-05-05 14:04:24 -07:00
mrg f48b0b8f41 Add left stripe power routes to tree router as option. 2021-05-05 13:45:12 -07:00
mrg d3f4810d1b Add error with zero length labels on GDS write. 2021-05-05 13:44:31 -07:00
mrg 2243761500 Must transitively cut blockages until no more. 2021-05-05 13:44:06 -07:00
Hunter Nichols 16904496ac Made path delays write out to the extended OPTS file. 2021-05-05 01:14:54 -07:00
mrg 19ea33d43d Move delay line module down. 2021-05-04 16:42:42 -07:00
Jesse Cirimelli-Low 1b53d12df2 don't double count spare col 2021-05-04 01:52:51 -07:00
Jesse Cirimelli-Low d0e9de1f13 fix port data spare col 2021-05-04 00:41:20 -07:00
Jesse Cirimelli-Low 93b264bc4c allow spare col number override 2021-05-03 21:59:05 -07:00
Jesse Cirimelli-Low a7d0a1ef3a remove breakpoint 2021-05-03 16:54:54 -07:00
Jesse Cirimelli-Low 14e087a5eb offset bank coordinates 2021-05-03 15:51:53 -07:00
mrg a0e263b14a Add vdd/gnd pins to the side. 2021-05-03 15:14:15 -07:00
Jesse Cirimelli-Low 4377619bf6 fixed port_data typo 2021-05-03 14:39:51 -07:00
Jesse Cirimelli-Low 31364e508e uncomment test (passing) 2021-05-03 13:08:04 -07:00
Jesse Cirimelli-Low d3199ea70e Merge branch 'dev' into laptop_checkpoint 2021-05-03 12:53:31 -07:00
Jesse Cirimelli-Low 64b1946d6e sky130 singlebank drc clean 2021-05-03 12:52:07 -07:00
Jesse Cirimelli-Low 3a3da9e0d7 56 drc errors on col mux 1port 2021-05-02 21:49:09 -07:00
mrg 98fb34c44c Add conditional power pins to Verilog model. 2021-04-30 14:15:32 -07:00
mrg fc6e6e1ec7 Add via when write driver supply is different layer 2021-04-28 15:16:26 -07:00
mrg 03e0c14ab2 Move write driver supply to m1 rather than pin layer 2021-04-28 10:13:33 -07:00
Jesse Cirimelli-Low 33e8bce79d dynamic predecode working 2021-04-25 01:22:36 -07:00
Jesse Cirimelli-Low 6ea4bdc5e5 Merge branch 'dev' into laptop_checkpoint 2021-04-23 22:50:23 -07:00
Jesse Cirimelli-Low 4ea0fcd068 support multi cell wide precharge cells 2021-04-23 22:49:29 -07:00
mrg 467aaa708d Add noninverting logic function to custom decoder cells. 2021-04-22 16:13:54 -07:00
mrg d018963866 Specify ImportError to see other errors 2021-04-22 16:13:32 -07:00
mrg 01f4ad7a11 Add sky130 config examples 2021-04-22 13:53:23 -07:00
mrg a111ecb74c Fix extra indent that made openlane fail. 2021-04-22 13:05:51 -07:00
mrg 35fcb3f631 Abstracted LEF added. Params for array wordline layers. 2021-04-22 09:44:25 -07:00
mrg 15b0583ff2 Add custom parameter for wordline layer 2021-04-22 09:42:49 -07:00
Hunter Nichols b8c7fcf182 Removed measurement check which conflicts with multiport memories 2021-04-21 15:53:27 -07:00
mrg 419836411c Fix missing via for global wordlines. 2021-04-21 11:33:18 -07:00
mrg f45efe3db6 Abstracted LEF added. Params for array wordline layers. 2021-04-21 11:04:01 -07:00
mrg 584349c911 Add custom parameter for wordline layer 2021-04-21 11:04:01 -07:00
mrg 9b40102bbb v1.1.15 2021-04-19 11:54:35 -07:00
mrg 439003e203 Respect the bus spacing parameter in predecoder. 2021-04-19 10:51:16 -07:00
Hunter Nichols 5dad0f2c0e Merged with dev, fixed import conflict in lib 2021-04-18 23:59:35 -07:00
mrg 5b556e6ef5 Update unit test results with new Verilog models. 2021-04-15 15:48:20 -07:00
mrg aa5e1fd168 Merge remote-tracking branch 'olofk/verilog_model_features' into dev 2021-04-15 14:41:56 -07:00
Olof Kindgren 688a1f1e60 Add HOLD_DELAY parameter for dout in verilog model 
Signed-off-by: Olof Kindgren <olof.kindgren@gmail.com>
 2021-04-15 22:39:49 +02:00
Olof Kindgren 1d657abebc Add VERBOSE parameter to generated verilog model 
This allows disabling the $display commands that are generated for every
read and write access to the model. The verilog output has been tested
with the following example script

from compiler.base.verilog import verilog

v = verilog()

v.num_words = 256
v.word_size = 32
v.write_size = 8
v.name = "sky130_sram_1kbyte_1rw1r_32x256_8"
v.all_ports = [0,1]
v.readwrite_ports = [0]
v.read_ports = [0,1]
v.write_ports = [0]
v.addr_size=8

v.verilog_write("mymodule.v")

Signed-off-by: Olof Kindgren <olof.kindgren@gmail.com>
 2021-04-15 22:33:57 +02:00
Jesse Cirimelli-Low e976c4043b Merge branch 'dev' into laptop_checkpoint 2021-04-14 15:58:06 -07:00
Jesse Cirimelli-Low 2f1d7b879f make bank compatable with sky130 2021-04-14 15:09:25 -07:00
mrg 41226087ba Use separate mXp pin layer if it exists 2021-04-14 13:55:21 -07:00
mrg 3eed6bb8ff Check for None before checking DRC tool 2021-04-14 11:07:38 -07:00
mrg a730fd0f10 Use magic for LEF abstract. Fix supply perimter pin. 2021-04-14 10:01:43 -07:00
mrg 0e48e020c1 Use pins in computing bbox offsets 2021-04-13 16:24:28 -07:00
mrg e706f776eb Offset macro to 0,0 which was accidentally comented by a PR 2021-04-13 16:24:13 -07:00
mrg b510925bdb Enable pruning by default (except on unit tests) 2021-04-07 16:08:29 -07:00
mrg 61b1b90dd3 Use built in binary conversion. Improve spare debug output. 2021-04-07 16:08:29 -07:00
mrg 229b0059c4 Add perimeter margin to expand pins outside perimeter for OpenRoad router. 2021-04-07 16:08:29 -07:00
mrg 5843aa037c Update functional test to use spare columns separately. 
Fix no spare columns data width error.
 2021-04-07 16:08:24 -07:00
mrg 0a02f635ad Remove lvs_write from sram 2021-04-07 16:08:24 -07:00
mrg d609e4ea04 Reimplement trim options (except on unit tests). 
Allow trim netlist to be used for delay and functional simulation.
Each class implements a "trim_insts" set of instances that can be removed.
By default far left, right, top and bottom cells in the bitcell arrays are kept.

Use lvs option in sp_write

Fix lvs option in sram.
 2021-04-07 16:07:56 -07:00
mrg 31d3e6cb26 Change LWL layers 2021-04-07 16:07:56 -07:00
mrg e0024fa79a Add verbosity to error output 2021-04-07 16:07:56 -07:00
mrg bd28a7a93b Merge branch 'sky130_fixes' into dev 2021-04-01 16:48:22 -07:00
mrg 014c95f761 Add accounting output to ngspice 2021-04-01 16:48:15 -07:00
mrg c7f99aef2c Add functional comment to aid debugging checks. 2021-03-31 12:14:20 -07:00
mrg 7e29dd7ff2 Reduce verbosity of routing info 2021-03-31 09:38:06 -07:00
mrg b9086dbbe5 Add unit test times to output. 2021-03-26 06:56:58 -07:00
mrg 6e2f60353c Add wells to driver stages. Remove unnecessary height/center in control logic. 2021-03-25 10:00:24 -07:00
mrg 4a40e96f6d Control logic route changes. 
Move wl_en to top control signal.
Route wl_en directly to port_address.
Reorder input bus to bank.
 2021-03-24 14:32:10 -07:00
mrg e144f03b23 Add status for supply routing. 2021-03-24 11:15:59 -07:00
mrg fae72ca993 Test new archive options for github actions. 2021-03-23 13:06:36 -07:00
mrg 7b270514e1 Update multithreaded regression. 
Only do 2 threads for 30 tests.
Don't archive results since they are purged anyways.
16 threads for regression.
Purge temp during regression.
 2021-03-23 10:45:56 -07:00
mrg 671470f5f2 Skywater changes. 
Default 1 thread and no temp subdirectory.
Add skywater setup/hold golden data
Add CLI option for simulation threads (-m)
Add compatibility mode option and nomodcheck for ngspice to speed up sky130 model loading.
Make subdir when using default /tmp dir.
Pass num_threads so temp subdirs are created.
 2021-03-22 15:48:14 -07:00
Hunter Nichols 6f01ab4792 Added simulation time modeling to regression model. 2021-03-22 12:55:29 -07:00
Hunter Nichols 208586a8e8 Added simulation time in the datasheet 2021-03-22 12:21:10 -07:00
mrg b6f3fbdd1f Use OPTS.precharge instead of hard coded precharge. 2021-03-15 09:44:14 -07:00
mrg db118beeba Zoom parameter should be optional in tech files. 2021-03-02 13:38:09 -08:00
Hunter Nichols 2cd3d28add linear regression model coefficients are now written to the extended config file 2021-03-02 13:14:56 -08:00
mrg 90cb9f581f Fixes to get hspice delay test to pass. 2021-03-02 09:28:41 -08:00
mrg fb953c19e8 Remove option that causes errors and is unused. 2021-03-01 16:36:27 -08:00
mrg 13bdae2e30 Merge remote-tracking branch 'private/dev' into control-logic-pull 2021-03-01 15:47:33 -08:00
mrg 049d3ffcaf Remove extra test file 2021-03-01 15:25:39 -08:00
mrg 9e7c04a43a Merge lekez2005 changes WITHOUT control logic change. 2021-03-01 15:19:30 -08:00
mrg f31125645e Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2021-03-01 14:06:51 -08:00
mrg 4ab694033d Merge remote-tracking branch 'bvhoof/dev' into dev 2021-03-01 12:16:26 -08:00
mrg ae8926c5c2 Merge remote-tracking branch 'private/dev' into dev 2021-03-01 12:12:44 -08:00
mrg 5ab67214e5 Make sure to add path when source and target 2021-03-01 11:37:42 -08:00
Bob Vanhoof f5a9ab3b2c cleanup clutter 2021-03-01 15:23:57 +01:00
Bob Vanhoof fde8794282 calibre pex modifications to run hierarchical pex 2021-03-01 09:56:25 +01:00
ota2 f6afef8d4a rbl_bl_delay_bar to rbl_bl_delay for write enable 2021-02-27 19:30:37 -05:00
ota2 9d025604ff Simulate calibre extracted netlists without requiring extra layout ports 2021-02-27 19:29:18 -05:00
ota2 9a2987ad07 Add spectre simulator 2021-02-27 19:25:00 -05:00
ota2 48bc47c686 Set pin label size to use zoom factor from tech specifications 2021-02-27 18:30:57 -05:00
mrg 0c2ed487d9 Redundant check if pin contains another 2021-02-26 11:16:19 -08:00
mrg 9f0ab0d081 Route perimeter signals before power grid 2021-02-26 11:14:39 -08:00
mrg 2a9b5db6d4 Rewrite enclose grids to be cleaner 2021-02-26 11:14:08 -08:00
Hunter Nichols d3ef1d7b85 Changed to ridge model to reduce effects of overfitting on small models. 2021-02-26 11:00:21 -08:00
Hunter Nichols b5516865f1 Added option to allow specific load/slew combinations in config file. 2021-02-24 16:43:34 -08:00
mrg 013836bb3d PEP8 cleanup 2021-02-23 13:33:14 -08:00
mrg 549112fcf8 PEP8 cleanup 2021-02-23 13:32:13 -08:00
mrg 1c6de4591d Remove vertical power pin vias. 2021-02-23 13:32:00 -08:00
Hunter Nichols 2ce802612b Stopped script from crashing if area is not included in the model dataset 2021-02-17 10:42:01 -08:00
Hunter Nichols ad1509b29b Added local_array_size as an input to the model 2021-02-17 10:00:11 -08:00
Hunter Nichols 3f5fd0b6f4 Merge branch 'dev' into automated_analytical_model 2021-02-15 15:20:49 -08:00
Hunter Nichols c7f14b1bf9 Removed stale fixme and moved words per row OPTS setting. 2021-02-15 15:20:32 -08:00
Hunter Nichols c308dd34a4 Merge branch 'dev' into elmore_model_tuning 2021-02-15 14:50:56 -08:00
mrg 33bc9a597c Remove dashes for Python module name warning. 2021-02-15 08:19:08 -08:00
mrg 506daaec99 Merge remote-tracking branch 'private/dev' into dev 2021-02-13 23:52:18 -08:00
mrg 7610f23fc7 Sub temp directory. Add github archive. 2021-02-10 15:39:12 -08:00
Hunter Nichols 4700f14e82 Removed area as an input feature to regression model 2021-02-10 14:20:38 -08:00
mrg b82b7aaf28 PEP8 format 2021-02-10 12:10:04 -08:00
mrg c78d3a9cca Merge branch 'dev' into runner_test 2021-02-10 11:17:35 -08:00
mrg 29c3d46be6 Warn about threads forced to 1 2021-02-10 10:23:06 -08:00
jcirimel f2d4794cc6 remove unused import 2021-02-09 21:01:16 -08:00
jcirimel b18e2eae8d remove debug lines and merge 2021-02-09 20:53:23 -08:00
jcirimel dbe8a7f1af fix pwell pin shape bug 2021-02-09 20:51:50 -08:00
Bob Vanhoof d14a68847e added cell label checker and cell labels to the freepdk technology 2021-02-09 13:09:26 +01:00
Bob Vanhoof 3dfc039f6f add technology option passtrough in test 30 2021-02-09 09:32:35 +01:00
mrg b83d93cc9a GitHub Actions CI flow. 2021-02-08 15:46:02 -08:00
Hunter Nichols f81c1ee4fc Contents of previous datasheet truncated if paths are the same 2021-02-05 16:51:35 -08:00
mrg e043aaffb3 Don't print DRC/LVS/PEX run stats in regress.py 2021-02-03 15:17:28 -08:00
mrg 19e99d1c7b Enable parallel regression testing. 2021-02-03 14:19:11 -08:00
Hunter Nichols df8d59f32e Merge branch 'dev' into automated_analytical_model 2021-02-01 01:49:45 -08:00
Hunter Nichols 7bed5bdd1c Added option for model to specify regression model data path. 2021-01-25 14:24:54 -08:00
mrg bc8fd4a882 Merge branch 'supply_router' into dev 2021-01-25 11:01:48 -08:00
Matt Guthaus eebc2a93b6 Remove redundant pins when adding each pin 2021-01-25 09:36:27 -08:00
Matt Guthaus 30fc81a1f0 Update copyright year. 2021-01-22 11:23:28 -08:00
Hunter Nichols e26e17c53f Added option to specify exact corners for characterization in config file 2021-01-22 00:50:28 -08:00
mrg db142bcd5a Rename pins to original names 2021-01-21 15:22:54 -08:00
Hunter Nichols d1b240dfb5 Added nom_voltage, etc back but changed values to replicate the operating conditions. Readded nom values back in golden files. 2021-01-21 13:52:55 -08:00
Hunter Nichols 31ad1963f6 Removed nominal pvt corners from golden lib files. 2021-01-21 12:47:18 -08:00
mrg b3e249c722 Merge remote-tracking branch 'private/dev' into dev 2021-01-20 12:36:04 -08:00
Hunter Nichols b0c2722583 Changed lib file to only contain reference to the operating voltage and removed nominal voltage references. 2021-01-19 15:22:50 -08:00
Hunter Nichols 70fe90f0af Added shared classes between regression models, added and changed some debug messages 2021-01-19 14:19:50 -08:00
Hunter Nichols 6d2a35e929 Changed most lists to dict to reduce hardcoded indices 2021-01-19 13:47:54 -08:00
mrg 608e4b81f1 Merge remote-tracking branch 'private/dev' 2021-01-15 16:11:23 -08:00
mrg 3048c61c20 Merge branch 'supply_router' into dev 2021-01-15 14:28:08 -08:00
mrg e8239c5e77 Remove debug print statement 2021-01-15 14:27:54 -08:00
mrg 69fe050bad Refactor and cleanup router grids. 2021-01-15 13:25:57 -08:00
mrg 683f4214b2 Differentiate pin and other blockages for easier to understand blockage processing. 2021-01-14 15:58:37 -08:00
Hunter Nichols 7259c197d8 Merge branch 'dev' into automated_analytical_model 2021-01-13 14:18:18 -08:00
Hunter Nichols 1881d43948 Added initial neural network model 2021-01-13 14:07:52 -08:00
mrg e3a888e0f7 Only unblock blockages not grids 2021-01-13 13:57:49 -08:00
mrg 88f2198524 Always use min area power/IO pins 2021-01-13 13:56:46 -08:00
mrg 3ef56a29ea Bug fix 2021-01-13 13:56:22 -08:00
Hunter Nichols ed3d39a1b8 Added updated model data with slews and loads. Changed linear regressions to account for additional models. 2021-01-13 13:04:34 -08:00
mrg 1b31afd773 Use partial grids for enclosure with note 2021-01-13 13:01:55 -08:00
mrg bc9ab086e5 Clean up imports 2021-01-13 13:01:33 -08:00
mrg 78966824db Second iteration try unblocking partial blocked grids. 2021-01-13 12:37:29 -08:00
mrg 4991693f1a Clean up min area 2021-01-13 12:32:17 -08:00
mrg 01d312d65c Refactor add power pins 2021-01-13 10:57:12 -08:00
mrg 408ea15228 Ordering bug fixed in Magic. 2021-01-12 16:20:26 -08:00
mrg 6f5b7c0264 Flatten bug fixed in Magic so don't flatten routes. 2021-01-12 16:20:03 -08:00
mrg 3d7bed0641 Fix typo in comment 2021-01-12 11:22:11 -08:00