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OpenRAM
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2633 Commits

Author SHA1 Message Date
mrg 17504a7da3 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2020-08-18 09:01:41 -07:00
mrg bc974ff78e Update replica column unit tests for new refactor 2020-08-18 08:56:24 -07:00
jcirimel 9cecf367ee Merge branch 'dev' into pex 2020-08-17 17:49:41 -07:00
jcirimel 714b57d48e Merge branch 'dev' into pex 2020-08-17 17:48:21 -07:00
mrg 99e252d6d4 Update interface of RBL array 2020-08-17 17:19:07 -07:00
mrg b1e55f9072 Add local bitcell array 2020-08-17 15:14:42 -07:00
mrg 3a692e2846 Comment updates 2020-08-17 14:35:39 -07:00
mrg 60224b105f Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2020-08-17 14:20:34 -07:00
mrg 94bfad4113 Horizontal gnd vias for unused array inputs 2020-08-17 13:24:34 -07:00
mrg bddb251a84 More room for power contacts 2020-08-17 12:32:44 -07:00
mrg 2c43d315db Revert gds readonly true 2020-08-17 12:19:23 -07:00
mrg 35a1b00aa0 Extra space for unused wl contacts 2020-08-14 14:23:40 -07:00
mrg 170e3feb7d Fix order of replica wordlines and bitlines 2020-08-14 14:14:49 -07:00
mrg 604e433e22 Add readonly true for Magic scripts 2020-08-14 10:40:31 -07:00
mrg 2ac04efe2e Must connect for replica cells other than top/bottom 2020-08-13 16:26:19 -07:00
jcirimel e7c9914d77 decoder passing except for bus route 2020-08-13 16:20:39 -07:00
mrg 797c41c750 Skip local bitcell array test 2020-08-13 14:36:39 -07:00
mrg 50525e70f4 Fix up to SRAM level with new replica bitcell array ports. 2020-08-13 14:29:10 -07:00
mrg 8dbaa66aa5 Merge branch 'super' into dev 2020-08-12 14:25:13 -07:00
mrg 7ac4574e4f Use micron units for all simulation in sky130 2020-08-12 13:54:55 -07:00
mrg 5fc6438553 Fix pinv_dec super call 2020-08-12 13:22:28 -07:00
mrg 15c8c200f3 Undo super() in measurement abstract class 2020-08-12 12:10:12 -07:00
mrg 55814a8f74 Fix syntax errors in pgates for super edits 2020-08-12 11:15:32 -07:00
mrg 0bec6f0439 Fix SRAM to use simulation spice instead of LVS spice 2020-08-12 10:41:21 -07:00
mrg a55909930f Replace replcia_bitcell_array with new one in bank 2020-08-12 09:49:14 -07:00
mrg 8e890c2014 Replica bitcell with all the fixings 2020-08-11 15:00:29 -07:00
mrg 30976df48f Change inheritance inits to use super 2020-08-06 11:33:26 -07:00
mrg eef97ff215 Reabstracting bit and word line names. 2020-08-06 11:17:49 -07:00
mrg 037de96989 Merge branch 'dev' into wlbuffer 2020-08-05 10:37:29 -07:00
mrg 528cb07635 Merge branch 'dev' into wlbuffer 2020-08-05 10:01:43 -07:00
jcirimel 38648027d0 fix pinv unit test 2020-08-04 04:40:20 -07:00
jcirimel 02e65a00ef update pex to work with dev changes 2020-08-03 17:14:34 -07:00
Bob Vanhoof 9b8ef5ef57 fix: generated pex file was not passed correctly to lib characterizer 2020-08-03 10:16:12 +02:00
Bob Vanhoof 487bb6c6e9 Merge branch 'dev' of github:VLSIDA/OpenRAM into CalibrePexFilesUpdate 2020-08-03 09:32:27 +02:00
jcirimel 3221b4ec57 update to new metal stack names 2020-07-31 05:27:19 -07:00
Bob Vanhoof dc55ededc1 fix regession tests after calibre fix 2020-07-31 12:51:34 +02:00
mrg 487027a9f2 Fix pex file names 2020-07-30 11:35:13 -07:00
mrg 8fa0065aaf Undo PR 82 changes -- broke unit test. 2020-07-30 11:09:19 -07:00
mrg a663d903c5 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2020-07-30 08:44:25 -07:00
Matt Guthaus 68387ec525
Merge pull request #84 from bvhoof/CalibrePexFilesUpdate 
calibrepex: file copy fix
 2020-07-30 08:40:35 -07:00
Hunter Nichols c6f2edc20d Changed warning message for multiport analytical characterization. 2020-07-29 19:50:06 -07:00
mrg 64d61f4d56 Merge remote-tracking branch 'private/dev' into dev 2020-07-29 12:16:41 -07:00
mrg f23d2e36a7 Don't obstruct control logic signals with dffs when no column mux. 2020-07-29 10:31:18 -07:00
mrg 8a2fa90cd5 Merge remote-tracking branch 'private/dev' into dev 2020-07-29 10:11:26 -07:00
mrg 2fa561f98f Local bitcell array edits. Skip test by default. 2020-07-29 10:08:13 -07:00
Hunter Nichols b4dafac489 Fixed issue with sen measurement not being added 2020-07-27 23:55:03 -07:00
mrg c260297366 Allow replica_bitcell_array without the replica columns for local wordlines. 2020-07-27 16:22:21 -07:00
Hunter Nichols 9ea3616260 Changed multiport characterization warning to better fit 2020-07-27 15:47:02 -07:00
Hunter Nichols c65178f86c Fixed issue with sen delay measure getting mixed with voltage checks 2020-07-27 15:43:50 -07:00
mrg 69cab42676 Add pbuf_dec gate 2020-07-27 13:59:55 -07:00
mrg 26b01e37c6 Fix pbuf test info 2020-07-27 13:59:35 -07:00
mrg 2991534d3f Drafting local bitline stuff. 2020-07-23 17:15:39 -07:00
mrg e1967dc548 Draft local and global arrays. Ensure rows before cols in usage. 2020-07-23 14:43:14 -07:00
mrg 317662d4aa Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2020-07-23 14:17:52 -07:00
mrg b7c43ae674 Fix 1w/1r example 2020-07-23 14:17:13 -07:00
jcirimel 1d9296ceb1 fix magic.py conflict 2020-07-21 11:50:25 -07:00
jcirimel df4a231c04 fix merge conflicts 2020-07-21 11:38:34 -07:00
mrg 58846a4a25 Limit wordline driver size. Place row addr dff near predecoders. 2020-07-20 17:57:38 -07:00
mrg 0ed81aa923 Removed extraneous shift from added mirroring 2020-07-20 14:11:52 -07:00
mrg 82bbacdfb5 Add data bus gap to dynamically computed channel width 2020-07-20 13:43:57 -07:00
mrg a36e89e103 Replace data flops depending on channel width 2020-07-20 13:26:05 -07:00
mrg 2ccf3aea3b Set channel route height and width (of routes, not pins) 2020-07-20 13:25:47 -07:00
mrg f87b427f76 Add parent to channel route for dumpign debug gds. 2020-07-20 12:03:25 -07:00
mrg f35848e4f8 Route col flops separately. Flip port 1 col flop for easier routing. 2020-07-20 12:02:59 -07:00
mrg 7385decbff Add channel route cyclic VCG debugging. 2020-07-20 12:02:30 -07:00
mrg 9d5d632d1a Pins may be below the channel. 2020-07-16 14:23:48 -07:00
mrg ba3d32fa0c Starting to implement minimizing channel router (not done) 2020-07-16 13:21:44 -07:00
mrg 919e6a5027 Merge remote-tracking branch 'private/dev' into dev 2020-07-15 19:47:44 -07:00
mrg c7bc01c3a9 Clean up binning. Fix mults to 1 for certain gates. 2020-07-15 17:15:42 -07:00
Bob Vanhoof ee3da91232 calibrepex: file copy fix 2020-07-15 11:50:21 +02:00
mrg bb8157b3b7 Exit on DRC not run, check for LVSDRC before running in sram_base. 2020-07-14 08:38:49 -07:00
mrg ed9d32c7bc OpenRAM 1.1.6 2020-07-13 16:26:25 -07:00
mrg e502ee02be Place before computing height of col mux. 2020-07-13 15:51:46 -07:00
mrg 2b7d89d2c1 Fix netlist_only in sky130 2020-07-13 14:59:31 -07:00
mrg e49236f8fc Default drc and lvs errors is skipped. 2020-07-13 14:08:00 -07:00
mrg 716798baae Convert all DRC and LVS routines to set member variables for drc_errors and lvs_errors. 2020-07-13 13:01:00 -07:00
mrg 2011974e01 Make drc and lvs errors a member variable. Run only once. 2020-07-13 12:49:24 -07:00
mrg a3195c0827 Add words_per_row and others in config file. 2020-07-13 12:37:56 -07:00
mrg a989ea63a0 Move magic/netgen files to tech dir 2020-07-09 11:33:14 -07:00
mrg 27166c75f0 Don't remove temp files during regular openram runs. 2020-07-03 07:00:56 -07:00
mrg 5dde466ab9 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2020-07-03 06:55:45 -07:00
mrg 282f944b2f Also write .lvs file since it can be different the .sp 2020-07-03 06:55:35 -07:00
Hunter Nichols 206b02a7ee Merge branch 'dev' into characterizer_bug_fixes 2020-07-02 18:00:41 -07:00
Hunter Nichols fb34338fdf Removed debug statements 2020-07-02 18:00:02 -07:00
Hunter Nichols 119bd94689 Fixed warnings with single port characterization. Cleaned up some signal names. 2020-07-02 15:43:23 -07:00
mrg d48f483248 Fix swapped instance bug in perimeter pins. 2020-07-01 15:10:20 -07:00
mrg bed2e36550 Simplify write mask supply via logic 2020-07-01 14:44:48 -07:00
mrg 8cd1cba818 Fix missing via in wmask driver 2020-07-01 14:44:18 -07:00
mrg c340870ba0 Channel route dout wires as well in read write ports 2020-07-01 14:44:01 -07:00
mrg bb18d05f75 Move control output via inside module instead of perimeter 2020-07-01 11:33:25 -07:00
mrg 3d0f29ff3a Fix missing via LVS issues. LVS passing for some 20 tests. 2020-07-01 09:22:59 -07:00
mrg b07f30cb9e Missing output via in control logic 2020-06-30 16:23:07 -07:00
mrg 3379f46da1 Fail unit test, but mention if LVS passes and DRC fails. 2020-06-30 16:22:44 -07:00
mrg 0a87691176 Run Calibre LVS even if DRC fails. 2020-06-30 15:27:10 -07:00
mrg c1fedda575 Modifications for min area metal. 
Made add_via_stack_center iterative instead of recursive.
Removed add_via_stack (non-center) since it isn't used.
Add min area metal during iterative via insertion.
 2020-06-30 15:07:34 -07:00
mrg 011ac2fc05 Don't route to clk to perimeter on m2 2020-06-30 13:57:45 -07:00
mrg a48ea52253 Add missing contact to vdd pins. 2020-06-30 13:26:38 -07:00
mrg 5626fd182e Extra track in data bus. Remove old code. 2020-06-30 10:58:24 -07:00
mrg eb11ac22f3 Widen pitch of control bus in bank. 2020-06-30 10:58:09 -07:00
mrg 8cedeeb3d9 Widen pitch of control bus in bank. 2020-06-30 10:57:41 -07:00
Matt Guthaus 9b939c9a1a DRC/LVS and errors fixes. 
Only enact pdb if assert fails in debug.error.
Only run drc/lvs one time in parse_info by saving result.
Cleanup drc/lvs output.
 2020-06-30 07:16:05 -07:00
Hunter Nichols 0464e2df5d Allowed bitline checks for multiple ports. 2020-06-30 01:37:52 -07:00
Hunter Nichols c289637dab Allowed sen's from multiple ports to be characterized 2020-06-29 23:18:31 -07:00
mrg 372a8a728e Off by one error in channel spacing 2020-06-29 16:47:34 -07:00
mrg 459e3789b8 Change control layers in sky130. 2020-06-29 16:23:25 -07:00
mrg bec948dcc3 Fix error in when to add vias for array power 2020-06-29 15:28:55 -07:00
mrg 4e7e0c5954 Skip test in sky130 2020-06-29 15:28:16 -07:00
Matt Guthaus e97644c424 Only do reverse lookup on valid interconnect layers since layer numbers can be shared. 2020-06-29 14:42:24 -07:00
mrg 07d0f3af8e Only copy end-cap pins to the bank level 2020-06-29 11:46:59 -07:00
mrg 1bc0775810 Only add pins to periphery 2020-06-29 10:03:24 -07:00
mrg 5f3a45b91b Compute bus size separately for ports 2020-06-29 05:54:30 -07:00
mrg 47f541df0e Fix bugs in channel route. 2020-06-28 16:58:28 -07:00
mrg 5285468380 All bitcells need a vdd/gnd pin 2020-06-28 15:09:47 -07:00
mrg 751eab202b Move row addr flops away from predecode. Route spare wen separately on lower layer. 2020-06-28 15:06:29 -07:00
mrg 051c8d8697 Only add bitcells to dummy and replica rows and columns (the perimeter) 2020-06-28 14:47:54 -07:00
mrg 709535f90f Fix right perimeter pin coordinate bug 2020-06-28 14:47:17 -07:00
mrg 225fc69420 Use preferred routing direction 2020-06-28 14:29:12 -07:00
mrg 4df02dad67 Move spare wen_dff to the right by spare columns 2020-06-28 14:28:43 -07:00
mrg bc3de9db05 Pick correct side of pin in channel route. 2020-06-28 14:28:18 -07:00
mrg 0c9f52e22f Realign col decoder and control by 1/4 so metal can pass over 2020-06-28 07:15:06 -07:00
mrg 66ea559209 Use channel for dffs all at once 2020-06-27 08:23:12 -07:00
mrg c10a6a29c0 Simplify precharge pin layer 2020-06-27 08:22:16 -07:00
mrg 609aa98c8b Move write mask pin to left of cell to avoid sense amp 2020-06-27 08:21:53 -07:00
mrg 2bd498c39c Change precharge layer to m3 2020-06-27 08:21:30 -07:00
mrg c07e20cbe4 Move mux select from li to m2 in sky130 2020-06-26 14:27:16 -07:00
mrg 94d7000717 Reduce output clutter from gds write 2020-06-26 12:16:54 -07:00
mrg f57eeb88eb PEP8 cleanup, multiple vdd/gnd support 2020-06-26 11:47:55 -07:00
mrg e23d41c1d4 PEP8 cleanup 2020-06-26 11:47:35 -07:00
mrg 567675ab31 PEP8 cleanup 2020-06-26 11:47:12 -07:00
mrg af4ed3dd6e Skip riscv func test for time sake 2020-06-26 06:50:45 -07:00
mrg d53abba479 Always route the channel route since it is it's own design. 2020-06-25 17:43:44 -07:00
mrg 76e5389c33 Change riscv func test name 2020-06-25 17:43:17 -07:00
mrg 9eb1b500ea Skip phys riscv test 2020-06-25 17:31:23 -07:00
mrg f11afaa63d Refactor channel route to be a design. 2020-06-25 17:30:03 -07:00
mrg 7220b23402 Add riscv unit tests 2020-06-25 15:34:18 -07:00
mrg 66df659ad4 Col decoders are anything not bitcell pitch. 2020-06-25 14:25:48 -07:00
mrg f84ee04fa9 Single bank passing. 
Parameterized gate column mux of dff height.
End-cap only supply option instead of no vdd in bitcell.
 2020-06-25 14:03:59 -07:00
mrg ee0a003298 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2020-06-25 08:57:37 -07:00
jcirimel 5941e01b51 add missing parens 2020-06-25 08:02:08 -07:00
jcirimel 59562f2b92 move accuracy_requirement from techfile to config 2020-06-25 06:44:07 -07:00
jcirimel 812cf11e95 Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into dev 2020-06-25 06:32:29 -07:00
jcirimel 57b6d49edb fix pinv size bining 2020-06-25 06:32:07 -07:00
mrg da900b89ba Only expand implants in sky130 2020-06-24 13:48:30 -07:00
mrg ba92467fec Add no well enclosure for techs without wells 2020-06-24 12:07:47 -07:00
mrg 6c523a7556 use add_enclosure for npc contacts 2020-06-24 11:55:44 -07:00
mrg e694622f28 use add_enclosure to extend implants 2020-06-24 11:54:59 -07:00
mrg 4bc3df8931 Add get_tx_insts and expand add_enclosure 2020-06-24 11:54:36 -07:00
mrg 93d65e84e1 Fix power pin layer problems in delay line 2020-06-24 10:26:49 -07:00
mrg 98ec9442c6 Add npc enclosure for pnand2, pnand3, pnor2 2020-06-24 10:00:00 -07:00
mrg 1340908330 Remove fudge factor for pin spacing 2020-06-24 09:24:26 -07:00
mrg cddb16dabc Separate active and poly contact to gate rule 2020-06-24 09:17:39 -07:00
mrg a32b5b13e8 Rename nwell yoffset for consistency 2020-06-24 08:26:15 -07:00
mrg b3d1161957 Add u+x permissions to new tests 2020-06-24 08:19:25 -07:00
Joey Kunzler 22ed725a35 made 1rw_1r tests for write driver and wmask, fixed typo in portdata_wmask_1rw_1r_test 2020-06-23 18:16:14 -07:00
Joey Kunzler 4e83e8c648 added contact to locali for wmask 2020-06-23 18:13:17 -07:00
mrg 22c821f5d8 Change port_address test to 256 for riscv 2020-06-23 15:40:00 -07:00
mrg cfa234a4d0 Extra space between decoders for well spacing 2020-06-23 15:39:42 -07:00
mrg 83001e1ab5 PEP8 formatting 2020-06-23 15:39:26 -07:00
mrg e849a9b973 Use different LVS libs based on tech and sky130 2020-06-23 14:53:24 -07:00
mrg 031862c749 Add metal enclosure to base case of center via stack. 2020-06-23 11:56:50 -07:00
mrg 1a528f9739 Skip and4_dec test 2020-06-23 10:08:28 -07:00
mrg 7ea3366ef1 Disable magic filter in sky130 2020-06-22 16:58:01 -07:00
mrg 92fc30005c Use factory in and_dec tests 2020-06-22 16:55:49 -07:00
mrg 40edbfa51f Error out on single port in sky130 2020-06-22 15:41:59 -07:00
mrg cd23b31ab4 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2020-06-22 12:55:45 -07:00
mrg 0926eab9f5 PEP8 formatting 2020-06-22 12:55:18 -07:00
mrg 54120f8405 Add option for removing subckt/instances of cells for row/col caps 2020-06-22 12:35:37 -07:00
mrg a13d535945 PEP8 cleanup 2020-06-22 11:33:02 -07:00
Joey Kunzler 8166adc512 Merge branch 'dev' into s8_update 2020-06-19 15:35:49 -07:00
Joey Kunzler 208c652653 added error for sky130 with invalid x mirroring (for lvs) 2020-06-19 13:59:33 -07:00
mrg a2d160dbf5 Copy magic config for filter code 2020-06-19 13:40:45 -07:00
mrg 5872f553e1 Rename tests for consistency 2020-06-19 08:53:35 -07:00
mrg 239b3ea007 Make wmask test a 1rw/1r 2020-06-19 08:49:48 -07:00
mrg 617a84d4b8 Fix output name of magic gds filter 2020-06-19 07:15:27 -07:00
mrg 94c480911b ngspice raw save doesn't work with measures 2020-06-19 07:09:15 -07:00
mrg 231f90f492 Fix missing space in ptx spice line 2020-06-19 06:47:46 -07:00
mrg 403ea17039 PEP8 formatting 2020-06-18 14:55:01 -07:00
mrg 69f5621245 Save raw file from ngspice 2020-06-18 14:54:36 -07:00
mrg 7dfc462ef6 Add magic filter before calibre for sky130 2020-06-15 13:58:26 -07:00
mrg abb5ff7bae Separate route conditions for s8 2020-06-15 10:30:27 -07:00
mrg e331d6fae8 Permute bus order to avoid conflict in control_logic 2020-06-15 10:25:53 -07:00
mrg a862cf3cb2 Test more single level col mux configs 2020-06-15 10:17:54 -07:00
mrg 4cb827c3d7 Add redundant implant for s8 2020-06-15 10:08:07 -07:00
mrg 355474ce2c Playing around with pnand2 pin spacing rules 2020-06-15 10:07:00 -07:00
mrg 6e0008403e Update new tech name 2020-06-15 10:06:17 -07:00
mrg 79b3b9a8b0 Switch input/output layers for predecodes 2020-06-15 10:06:04 -07:00
mrg 6c04166876 Update port data wmask tests 2020-06-15 06:05:05 -07:00
mrg 02352c35d7 Fix hard coded layer in wmask 2020-06-14 17:10:32 -07:00
mrg 52ee7b0a19 Disable perimeter pins and make an option 2020-06-14 16:44:10 -07:00
mrg 78be9f367a Add brain-dead router pins to perimeter 2020-06-14 15:52:09 -07:00
mrg 9930b5f3f6 Do not run tapless unit tests 2020-06-14 14:18:25 -07:00
mrg 7dc33285a7 Add contact to gate design rule to max for spacing inputs 2020-06-14 14:18:08 -07:00
mrg 8e8a97cc4b Add correct boundary to SRAM 2020-06-14 14:17:35 -07:00
mrg 443c401561 pnand2 B input spaced from top 2020-06-14 14:17:04 -07:00
mrg 91f20f2cf6 Better centering of pinv_dec 2020-06-14 14:09:45 -07:00
mrg 8f1dc7eeea Include mirror/rotate on translate_all boundary update 2020-06-13 06:50:53 -07:00
mrg 33a32101c9 DRC and LVS fixes for pinv_dec 2020-06-12 15:23:51 -07:00
mrg 443b8fbe23 Change s8 to sky130 2020-06-12 14:23:26 -07:00
mrg 54e4d147f6 Rail to ptx spacing based on routing layer not m1 2020-06-11 15:03:50 -07:00
mrg e9780ea599 Add non-preferred directions for channel routes 2020-06-11 15:03:36 -07:00
mrg 8d52794c32 Remove printf in precharge 2020-06-11 11:57:52 -07:00
mrg 7ad2d54a69 Add pin and label purposes 2020-06-11 11:54:51 -07:00
mrg 1a2e0046b1 Add contact to gate spacing for precharge 2020-06-11 11:54:34 -07:00
mrg 089331ced3 Add stdc bounding box too 2020-06-11 11:54:16 -07:00
mrg 098219d56c Add npc enclosure to poly contacts 2020-06-11 11:53:59 -07:00
mrg f973dd6a5c Save LVS model with no u too for Calibre 2020-06-11 11:53:34 -07:00
mrg dff28a9997 Merge branch 'tech_migration' into dev 2020-06-10 17:09:05 -07:00
mrg 196e5998c8 Half poly space per cell at top and bottom. 2020-06-10 16:52:51 -07:00
mrg fdf92d0da1 Rename test 14 2020-06-10 16:41:26 -07:00
mrg 0b4b5e7133 More exact input spacing in pnand3 2020-06-10 16:19:24 -07:00
mrg bfd1abc79f Replica column pins start at 0 height. 2020-06-10 14:58:55 -07:00
mrg 469cd260b9 Change bitcell array name to match 2020-06-10 14:54:20 -07:00
mrg f2c45a230e Add new replica column test. Add more skip tests. 2020-06-10 11:00:00 -07:00
mrg 10be2d08b5 Full path to skip tests file 2020-06-10 10:23:05 -07:00
mrg 5e3332453b Allow power pins to start on any layer besides m1 2020-06-10 10:15:23 -07:00
mrg c119e60e79 Add more s8 skip tests 2020-06-10 10:14:52 -07:00
mrg d4fc88124a Rename dff_buf test 2020-06-09 17:18:19 -07:00
mrg 064fe34edf Fix pinvbuf layers 2020-06-09 17:16:35 -07:00
mrg 14782914b3 Remove vertical pand gates 2020-06-09 16:40:59 -07:00
mrg e6babc301d Incrase space for pnand gates 2020-06-09 16:34:15 -07:00
mrg c6b875146d Use local skip file 2020-06-09 16:33:59 -07:00
mrg fd49d3ed6a Add tech specific skip tests for making new techs. 2020-06-09 16:09:15 -07:00
mrg 580b0601b5 Unskip 20_psram_1bank_4mux_1rw_1r_test 2020-06-09 16:04:39 -07:00
mrg a28e747a02 Fix precharge offset. Move well rules to design class. 2020-06-09 15:28:50 -07:00
mrg 148521c458 Remove stdc layer 2020-06-09 13:48:47 -07:00
mrg 157926960b Flip freepdk45 flop, dff_buf route layer change 2020-06-09 13:48:16 -07:00
mrg 8c6d5b49be Consider diffusion spacing in active offset 2020-06-09 13:09:52 -07:00
mrg 77fb7017c4 Merge branch 'tech_migration' into dev 2020-06-08 12:54:41 -07:00
mrg 9cc36c6d3a Bus code converted to pins. Fix layers on control signal routes in bank. 2020-06-08 11:01:14 -07:00
Aditi Sinha c39c0efd39 Updated spare col tests 2020-06-08 16:38:18 +00:00
Aditi Sinha 300522a1a8 Change spare enable pins offset to lower right 2020-06-08 14:31:46 +00:00
Aditi Sinha ef940e0dc5 Fixes for functional test of spare cols 2020-06-08 05:02:04 +00:00
Aditi Sinha d5041afebc Merge branch 'dev' into bisr 2020-06-07 16:27:25 +00:00
jcirimel 5d5ed552e3 Merge branch 'dev' into discrete_models 2020-06-06 01:48:06 -07:00
mrg 0837432d45 Wordline route layers and (optional) via. 2020-06-05 16:47:22 -07:00
jcirimel 9857a3f7e7 Merge branch 'dev' into discrete_models 2020-06-05 16:47:01 -07:00
mrg 5514996708 Auto-generate port dependent cell names. 2020-06-05 15:09:22 -07:00
mrg 00b51f5464 PEP8 format replica_bitcell_array 2020-06-05 13:49:32 -07:00
mrg 4fef632dce Fix syntax error 2020-06-05 12:13:41 -07:00
mrg a62b85a6b1 Update mirroring in port_data for bitcell mirrored arrays 2020-06-05 11:29:31 -07:00
mrg 2e7f9395f2 Rename 05 test to 14 2020-06-05 09:57:16 -07:00
mrg 68ffb94d2e Rename 05 test to 14 2020-06-05 09:55:57 -07:00
mrg fb3acae908 PEP8 format testutils. 2020-06-05 09:44:30 -07:00
jcirimel 08f6bd8d24 optimize tx binning for area 2020-06-05 02:53:03 -07:00
mrg e14deff3d1 Fixed offset in port_data 2020-06-04 16:03:39 -07:00
mrg 2fcecb7227 Variable zjog. 512 port address test. s8 port address working. 2020-06-04 16:01:32 -07:00
mrg e06dc3810a Move precharge pin to bottom 2020-06-04 12:12:19 -07:00
mrg 717188f85c Change L shape of rbl route 2020-06-04 11:03:39 -07:00
mrg 7aafa43897 Connect RBL to bottom of precharge cell 2020-06-04 10:22:52 -07:00
mrg 249b5355ba Adjust rbl route 2020-06-03 17:08:04 -07:00