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OpenRAM
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1799 Commits

Author SHA1 Message Date
jsowash 01bdea23ae Merge branch 'add_wmask' of https://github.com/VLSIDA/PrivateRAM into add_wmask 2019-09-03 11:50:57 -07:00
jsowash b5ca417b26 Added fix for column mux lib generation.: 2019-09-03 11:50:39 -07:00
jsowash 4a8ec7a687 Added 2 port test for wmask. 2019-09-03 11:49:37 -07:00
Matt Guthaus 69c5608b53 Allow gds to be written with supplies off. Fix extraction bug with new options. 2019-09-03 11:23:35 -07:00
jsowash e8435d0d83 Added test for picorv32 memory without characterization. 2019-08-30 11:24:20 -07:00
jsowash e3b42430bd Changed max_gap_size_wmask to take into account column ffs. 2019-08-29 17:09:17 -07:00
jsowash bbe235074c Added max gap size for wmask and edited max gap size for data ff's to take into account m3 spacing. 2019-08-29 16:41:58 -07:00
Matt Guthaus a78245786c Merge branch 'add_wmask' of github.com:VLSIDA/PrivateRAM into add_wmask 2019-08-29 16:06:39 -07:00
Matt Guthaus 7fe9e5704d Convert vcg and nets to ordered dict 2019-08-29 16:06:34 -07:00
jsowash 37116ce9d8 Increased spacing between wmask and data dffs. 2019-08-29 16:00:50 -07:00
jsowash c1906ade3f Removed A pin's via connection since it's created in the SRAM level and rearranged the SRAM flip flop creation. 2019-08-29 14:48:13 -07:00
jsowash af3d2af0ec Merge branch 'dev' into add_wmask 2019-08-29 12:56:11 -07:00
jsowash f13c8eae8d Moved column mux ff's to be horizontal with wmask flip flops and adjusted wmask AND array en pin location starting point. 2019-08-29 11:07:42 -07:00
jsowash 5099ff6f6c Changed A/Z pins to copy_layout_pin and made en (B) pin a single pin. 2019-08-29 09:01:35 -07:00
Matt Guthaus 64fc771fc4 Simplify is not None 2019-08-22 15:02:52 -07:00
Matt Guthaus ee2456f433 Merge branch 'add_wmask' into dev 2019-08-22 15:01:41 -07:00
Matt Guthaus bdf29c3a26 Fix non-preferred route width again. This time it is likely right. 2019-08-22 13:57:14 -07:00
Matt Guthaus 560d768010 Fix syntax error in router 2019-08-22 13:46:32 -07:00
Matt Guthaus afaa946f9c Fix width of non-preferred trunk wire 2019-08-22 12:03:38 -07:00
jsowash 27ec617315 Fixed M1.5 error in 8mux tests which came from pdriver. 2019-08-22 09:34:53 -07:00
Matt Guthaus 2ffdfb18a4 Fix trunks less than a pitch in channel route 2019-08-21 17:11:02 -07:00
jsowash a8df5528f9 Added 2 mux test for wmask. 2019-08-21 16:06:36 -07:00
Matt Guthaus 98f526427e Merge branch 'add_wmask' of github.com:VLSIDA/PrivateRAM into add_wmask 2019-08-21 15:33:03 -07:00
Matt Guthaus 9ada9a7dfa Fix pitch in channel router to support M3/M4. 2019-08-21 15:32:49 -07:00
jsowash 737e873923 Changed via direction for via1 in flip flops. 2019-08-21 14:49:54 -07:00
Matt Guthaus 9f54afbf2c Fix capitalization in verilog golden files 2019-08-21 14:29:57 -07:00
jsowash 980760b724 Add preferred direction to via1, routed between supply lines in wmask AND array, and only uses m3 for channel route with a write mask. 2019-08-21 14:02:57 -07:00
Matt Guthaus 5f3ffdb8ba Output name and version in help 2019-08-21 14:00:55 -07:00
Matt Guthaus d0f04405a6 Convert capital names to lower case for consistency 2019-08-21 13:45:34 -07:00
jsowash 4f01eeb3c1 Combined changes to the pin locations and vias. 2019-08-21 12:36:53 -07:00
jsowash c2015335b0 Fixed merge issues. 2019-08-21 11:54:22 -07:00
jsowash 4813c01d56 Moved dff's up and moved wmask_AND/wdriver pins left/down, respectively. 2019-08-21 11:50:28 -07:00
Matt Guthaus b0821a5a0e Re-add simplified power pins on edges 2019-08-21 11:42:56 -07:00
Matt Guthaus b94af3e3fd Add vias for new channel routes 2019-08-21 11:33:43 -07:00
Matt Guthaus f281510828 Merge branch 'add_wmask' of github.com:VLSIDA/PrivateRAM into add_wmask 2019-08-21 11:20:42 -07:00
Matt Guthaus 2b7025335c Use pand2 of correct size. Simplify width checking of AND array. 2019-08-21 11:20:35 -07:00
jsowash 43d45fba98 Moved pwr/gnd pins to the right of the rail. 2019-08-21 10:44:04 -07:00
Matt Guthaus c39b09c736 Merge branch 'add_wmask' of github.com:VLSIDA/PrivateRAM into add_wmask 2019-08-21 10:18:59 -07:00
Matt Guthaus 54ab9440db Use pdriver instead of pinv in pand gates. 2019-08-21 10:18:46 -07:00
jsowash 0cbc4a7acf Moved wmask dff above data dff and changed channel route to m3/m4 for data and m1/m2 for wmask. 2019-08-21 10:07:20 -07:00
Matt Guthaus 53d0544291 Minor cleanup and additional assertion checking. 2019-08-21 08:50:12 -07:00
Matt Guthaus f2568fec80 Change permissions on tests to +x. Add single bank wmask test. 2019-08-21 08:49:46 -07:00
jsowash 71af70a636 Moved pwr/gnd vias and corrected width boundary. 2019-08-20 09:14:23 -07:00
jsowash 316132a33c Sized inverter for number of driven write drivers. 2019-08-19 13:31:49 -07:00
jsowash c19bada8df Performed clean up and added comments. 2019-08-19 08:57:05 -07:00
jsowash a28c9fed8b Fixed bug for more than 2 wmasks and changed test to test 4 wmasks. 2019-08-16 14:27:44 -07:00
jsowash d02ea06ff2 Added method to route between the output of wmask AND array and en of write driver. 2019-08-16 14:12:41 -07:00
jsowash aaa1e3a614 Added change to route wmask en between driver and AND gates. Need to apply it to all cases. 2019-08-16 10:23:51 -07:00
jsowash 92e0671e15 Removed DRC error with AND array in freepdk45 and moved pin on en_{} pin in port data. 2019-08-15 12:36:17 -07:00
jsowash f0f811bad9 Added a condiitonal to only route wmask dff when there's a write size. 2019-08-14 12:40:14 -07:00
jsowash 858fbb062d Placed wmask dff and added connections for wmask pins. 2019-08-14 11:45:22 -07:00
jsowash 0d7170eb95 Created wmask AND array en pin to go through to top layer. 2019-08-14 09:59:40 -07:00
jsowash aa4803f3c4 Increased enable pin's width for larger # of column mux ways. 2019-08-11 15:25:05 -07:00
jsowash 2573b5f48b Fixed merge conflict. 2019-08-11 14:39:36 -07:00
jsowash d259efbcda Connected wdriver_sel between write_mask_and_array and write_driver_array. 2019-08-11 14:33:08 -07:00
Matt Guthaus e5618b88af Don't add sense amp to write only port. Fix write_and None define. 2019-08-11 08:46:36 -07:00
Matt Guthaus d56a972d61 Update ngspice tests due to new version 2019-08-10 17:59:30 -07:00
Matt Guthaus c09005dab9 Redo logic for detecting bad bitlines 2019-08-10 17:32:36 -07:00
Matt Guthaus 6cf7366c56 Gate sen during first half period 2019-08-10 16:30:02 -07:00
Matt Guthaus 8d6a4c74e7 Merge branch 'dev' into control_fix 2019-08-10 13:07:30 -07:00
Matt Guthaus 23676c0f37 Route bl in SRAM write ports too 2019-08-10 12:53:07 -07:00
Matt Guthaus 34d28a19e6 Connect wl_en in all ports to bank. 2019-08-10 12:30:23 -07:00
Matt Guthaus bac684a82a Fix control logic routing. 2019-08-10 08:53:02 -07:00
jsowash d5e331d4f3 Connected en together in write_mask_and_array. 2019-08-09 14:27:53 -07:00
Hunter Nichols 2573d4e7d0 Removed testing code from config file. 2019-08-08 19:27:44 -07:00
Hunter Nichols 1d22d39667 Uncommented tests that use model delays. Fixed issue in sense amp cin. 2019-08-08 18:26:12 -07:00
jsowash 49fffcbc92 Added way to determine length of en pin with wmask in write_driver_array and shortened en to width of driver. 2019-08-08 15:49:23 -07:00
Hunter Nichols d273c0eef5 Merge branch 'dev' into analytical_cleanup 2019-08-08 13:20:27 -07:00
jsowash 0cfa0ac755 Shortened write driver enable pin so that a write mask can be used without a col mux in layout. 2019-08-08 12:57:32 -07:00
jsowash 59e5441aef Added write mask to write driver array 2019-08-08 08:46:58 -07:00
Hunter Nichols 3c44ce2df6 Replaced analytical characterization with graph implementation. Removed most analytical delay functions used by old chacterizer. 2019-08-08 02:33:51 -07:00
Hunter Nichols fc1cba099c Made all cin function relate to farads and all input_load relate to relative units. 2019-08-08 01:57:04 -07:00
Matt Guthaus d36f14b408 New control logic, netlist only working 2019-08-07 17:14:33 -07:00
Matt Guthaus 275891084b Add pand3 2019-08-07 16:33:29 -07:00
Matt Guthaus c2655fcaa9 Update pnor2 to new placement logic 2019-08-07 16:01:05 -07:00
jsowash 9409f60237 Merge branch 'dev' into add_wmask 2019-08-07 09:42:55 -07:00
jsowash abb9af0ea8 Added layout pins for wmask_and_array 2019-08-07 09:33:19 -07:00
jsowash a6bb410560 Begin implementing a write mask layout as the port data level. 2019-08-07 09:12:21 -07:00
Hunter Nichols 6860d3258e Added graph functions to compute analytical delay based on graph path. 2019-08-07 01:50:48 -07:00
Matt Guthaus ae46a464b9 Undo delay changes. Fix bus order for DRC. 2019-08-06 17:17:59 -07:00
Hunter Nichols 2ce7323838 Removed all unused analytical delay functions. 2019-08-06 17:09:25 -07:00
Matt Guthaus a2f81aeae4 Combine rbl_wl and wl_en. Size p_en_bar slower than wl_en. 2019-08-06 16:29:07 -07:00
Hunter Nichols 2efc0a3983 Merge branch 'dev' into analytical_cleanup 2019-08-06 14:51:30 -07:00
Matt Guthaus ad35f8745e Add direction to pins of all modules 2019-08-06 14:14:09 -07:00
Matt Guthaus c3f38a5cac ngspice delays updated (again) 2019-08-05 16:09:27 -07:00
Matt Guthaus aae8566ff2 Update golden delays. Fix uninitialized boolean. 2019-08-05 15:45:59 -07:00
Matt Guthaus 4d11de64ac Additional debug. Smaller psram func tests. 2019-08-05 13:53:14 -07:00
Matt Guthaus e4532083da Increase stages and FO of fixed delay line. 2019-08-05 13:52:32 -07:00
jsowash a4a72a9639 Merge branch 'dev' into add_wmask 2019-08-01 13:49:52 -07:00
Matt Guthaus 7ba97ee0ba Fix missing port in control logic 2019-08-01 12:42:51 -07:00
Matt Guthaus 8771ffbfed Fix bug to add all p_en_bar to banks 2019-08-01 12:28:21 -07:00
Matt Guthaus ff64e7663e Add p_en_bar to write ports as well 2019-08-01 12:21:43 -07:00
Matt Guthaus a8d09acd40 Use ordered dict instead of sorting keys 2019-08-01 12:21:30 -07:00
jsowash e4d8ba90a5 Merge branch 'dev' into add_wmask 2019-08-01 12:07:14 -07:00
Matt Guthaus d403362183 Sort keys for random read address choice. 2019-08-01 11:32:49 -07:00
jsowash bb1627bcec Added test to end of w_mask_and_array so a regression test will be performed on it. 2019-07-31 14:59:33 -07:00
jsowash 9819b5356e Merge branch 'dev' into add_wmask 2019-07-31 14:43:48 -07:00
jsowash 774f08da51 Added layout pins to and test for write_mask_and_array. 2019-07-31 14:11:37 -07:00
Hunter Nichols b4ef0ec36d Removed unused characterization module. 2019-07-30 20:33:17 -07:00
Hunter Nichols 24b1fa38a0 Added graph fixes to handmade multiport cells. 2019-07-30 20:31:32 -07:00