luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 01:24:39 +02:00
Code Issues Packages Projects Releases Wiki Activity

technology switching working

Browse Source
This commit is contained in:
Jesse Cirimelli-Low
2026-03-17 11:44:20 -07:00
parent 53d53ec271
commit ffcbd51019
9 changed files with 35 additions and 858 deletions
Download Patch File Download Diff File Expand all files Collapse all files
compiler/tests/14_replica_bitcell_array_leftrbl_1rw_test.py
+2 -1
View File
@@ -23,10 +23,11 @@ class replica_bitcell_array_leftrbl_1rw_test(openram_test):
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 0
OPTS.num_w_ports = 0
openram.setup_bitcell()
debug.info(2, "Testing 7x5 replica array for 1rw cell with left replica column")
a = factory.create(module_type="replica_bitcell_array", cols=8, rows=8, rbl=[1, 0], left_rbl=[0])
a = factory.create(module_type="replica_bitcell_array", cols=7, rows=5, rbl=[1, 0], left_rbl=[0])
self.local_check(a)
openram.end_openram()
compiler/tests/Makefile
+4
View File
@@ -176,7 +176,11 @@ $(TEST_BASES):
@rm -rf results/$*
@rm -rf results/$*.*
@mkdir -p results/$*/tmp
ifdef TECH_FILE
@sh -c "python3 -u $(OPENRAM_DIR)/$(getfile).py -t $(gettech) -k -f $(TECH_FILE) -v $(ARGS) -p $(OPENRAM_DIR)/results/$* > $(OPENRAM_DIR)/results/$*.out 2>&1 && touch $(OPENRAM_DIR)/results/$*.ok || touch $(OPENRAM_DIR)/results/$*.bad"
else
@sh -c "python3 -u $(OPENRAM_DIR)/$(getfile).py -t $(gettech) -k -v $(ARGS) -p $(OPENRAM_DIR)/results/$* > $(OPENRAM_DIR)/results/$*.out 2>&1 && touch $(OPENRAM_DIR)/results/$*.ok || touch $(OPENRAM_DIR)/results/$*.bad"
endif
ifdef KEEP
@test -f $(TOP_DIR)/compiler/tests/results/$*.ok && echo "$* ... PASS!" || echo "$* ... FAIL!"
else