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Single bank working except for channel routing error in 4-way case.

This commit is contained in:
Matt Guthaus 2018-07-17 14:40:04 -07:00
parent 7a69fc1bca
commit ffc866ef78
2 changed files with 2 additions and 2 deletions
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2
compiler/modules/bank.py
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@ -380,7 +380,7 @@ class bank(design.design):
Create a 2:4 or 3:8 column address decoder. Create a 2:4 or 3:8 column address decoder.
""" """
# Place the col decoder right aligned with row decoder # Place the col decoder right aligned with row decoder
x_off = -(self.central_bus_width + self.wordline_driver.width) x_off = -(self.central_bus_width + self.wordline_driver.width + self.col_decoder.width)
y_off = -(self.col_decoder.height + 2*drc["well_to_well"]) y_off = -(self.col_decoder.height + 2*drc["well_to_well"])
self.col_decoder_inst=self.add_inst(name="col_address_decoder", self.col_decoder_inst=self.add_inst(name="col_address_decoder",
mod=self.col_decoder, mod=self.col_decoder,

2
compiler/sram_1bank.py
View File

@ -154,7 +154,7 @@ class sram_1bank(sram_base):
def route_col_addr_dff(self): def route_col_addr_dff(self):
""" Connect the output of the row flops to the bank pins """ """ Connect the output of the row flops to the bank pins """
bus_names = ["A[{}]".format(x) for x in range(self.word_size)] bus_names = ["A[{}]".format(x) for x in range(self.col_addr_size)]
col_addr_bus_offsets = self.create_horizontal_bus(layer="metal1", col_addr_bus_offsets = self.create_horizontal_bus(layer="metal1",
pitch=self.m1_pitch, pitch=self.m1_pitch,
offset=self.col_addr_dff_inst.ul() + vector(0, self.m1_pitch), offset=self.col_addr_dff_inst.ul() + vector(0, self.m1_pitch),