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Fix syntax error for module scope in row/col caps.

This commit is contained in:
mrg 2022-07-13 17:19:09 -07:00
parent d92c7a634d
commit ff7ceaf92d
4 changed files with 4 additions and 4 deletions
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2
compiler/modules/col_cap_bitcell_1port.py
View File

@ -16,7 +16,7 @@ class col_cap_bitcell_1port(bitcell_base):
"""
def __init__(self, name="col_cap_bitcell_1port"):
bitcell_base.bitcell_base.__init__(self, name, prop=props.col_cap_1port)
bitcell_base.__init__(self, name, prop=props.col_cap_1port)
debug.info(2, "Create col_cap bitcell 1 port object")
self.no_instances = True

2
compiler/modules/col_cap_bitcell_2port.py
View File

@ -16,7 +16,7 @@ class col_cap_bitcell_2port(bitcell_base):
"""
def __init__(self, name="col_cap_bitcell_2port"):
bitcell_base.bitcell_base.__init__(self, name, prop=props.col_cap_2port)
bitcell_base.__init__(self, name, prop=props.col_cap_2port)
debug.info(2, "Create col_cap bitcell 2 port object")
self.no_instances = True

2
compiler/modules/row_cap_bitcell_1port.py
View File

@ -16,7 +16,7 @@ class row_cap_bitcell_1port(bitcell_base):
"""
def __init__(self, name="row_cap_bitcell_1port"):
bitcell_base.bitcell_base.__init__(self, name, prop=props.row_cap_1port)
bitcell_base.__init__(self, name, prop=props.row_cap_1port)
debug.info(2, "Create row_cap bitcell 1 port object")
self.no_instances = True

2
compiler/modules/row_cap_bitcell_2port.py
View File

@ -16,7 +16,7 @@ class row_cap_bitcell_2port(bitcell_base):
"""
def __init__(self, name="row_cap_bitcell_2port"):
bitcell_base.bitcell_base.__init__(self, name, prop=props.row_cap_2port)
bitcell_base.__init__(self, name, prop=props.row_cap_2port)
debug.info(2, "Create row_cap bitcell 2 port object")
self.no_instances = True