mirror of https://github.com/VLSIDA/OpenRAM.git
rom base passing tests with top level routing
This commit is contained in:
Jacob Walker
parent
7c453e80be
commit
fef9902c45
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@ -1897,7 +1897,7 @@ class layout():
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elif add_vias:
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self.copy_power_pin(pin, new_name=new_name)
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def add_io_pin(self, instance, pin_name, new_name, start_layer=None):
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def add_io_pin(self, instance, pin_name, new_name, start_layer=None, directions=None):
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"""
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Add a signle input or output pin up to metal 3.
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"""
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@ -1907,7 +1907,7 @@ class layout():
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start_layer = pin.layer
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# Just use the power pin function for now to save code
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self.add_power_pin(new_name, pin.center(), start_layer=start_layer)
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self.add_power_pin(new_name, pin.center(), start_layer=start_layer, directions=directions)
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def add_power_pin(self, name, loc, directions=None, start_layer="m1"):
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# Hack for min area
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@ -108,3 +108,15 @@ class rom_address_control_array(design):
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self.route_horizontal_pins("vdd", insts=self.buf_insts, layer=self.route_layer)
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self.route_horizontal_pins("gnd", insts=self.buf_insts, layer=self.route_layer)
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tmp_pins = []
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for pin in self.get_pins("vdd"):
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edge = vector(pin.lx() + 0.5 * self.route_width, pin.cy())
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tmp_pins.append(self.add_layout_pin_rect_center("vdd_edge", layer=self.route_layer, offset=edge))
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self.copy_layout_pin_shapes("vdd")
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self.remove_layout_pin("vdd")
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for pin in tmp_pins:
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print("copying pin")
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self.copy_layout_pin(self, "vdd_edge", "vdd")
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self.remove_layout_pin("vdd_edge")
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@ -1,3 +1,4 @@
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2023 Regents of the University of California and The Board
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@ -108,13 +109,12 @@ class rom_bank(design):
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self.route_clock()
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self.route_array_outputs()
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self.place_top_level_pins()
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self.route_supplies()
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self.route_output_buffers()
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rt = router_tech(self.supply_stack, 1)
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init_bbox = self.get_bbox(side="ring",
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margin=rt.track_width)
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self.route_supplies(init_bbox)
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# We need the initial bbox for the supply rings later
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# because the perimeter pins will change the bbox
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# Route the pins to the perimeter
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@ -125,7 +125,7 @@ class rom_bank(design):
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margin=11*rt.track_width)
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self.route_escape_pins(bbox)
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self.route_supplies()
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def setup_layout_constants(self):
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@ -221,6 +221,7 @@ class rom_bank(design):
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module_name="rom_output_buffer",
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rows=self.word_size,
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fanout=4,
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tap_spacing=1,
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invert_outputs=True)
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@ -373,8 +374,8 @@ class rom_bank(design):
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# Route precharge to col decoder
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start = prechrg_control.center()
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mid1 = vector(self.control_inst.rx(), prechrg_control.cy())
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mid2 = vector(self.control_inst.rx(), col_decode_prechrg.cy())
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mid1 = vector(self.control_inst.rx() + self.interconnect_layer_pitch, prechrg_control.cy())
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mid2 = vector(self.control_inst.rx() + self.interconnect_layer_pitch, col_decode_prechrg.cy())
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end = col_decode_prechrg.center()
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self.add_path(self.route_stack[0], [start, mid1, mid2, end])
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@ -383,7 +384,7 @@ class rom_bank(design):
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offset=end)
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start = mid1
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mid1 = vector(self.control_inst.rx(), start.y)
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mid1 = vector(self.control_inst.rx() + self.interconnect_layer_pitch, start.y)
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mid2 = vector(mid1.x, col_decode_clk.cy())
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end = col_decode_clk.center()
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self.add_path(self.route_stack[0], [start, mid1, mid2, end])
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@ -438,7 +439,7 @@ class rom_bank(design):
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self.add_io_pin(self.control_inst, "clk_in", "clk")
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for i in range(self.word_size):
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self.add_io_pin(self.output_inv_inst, "out_{}".format(i), "dout[{}]".format(i))
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self.add_io_pin(self.output_inv_inst, "out_{}".format(i), "dout[{}]".format(i), directions="nonpref")
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for lsb in range(self.col_bits):
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name = "addr[{}]".format(lsb)
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@ -449,15 +450,49 @@ class rom_bank(design):
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pin_num = msb - self.col_bits
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self.add_io_pin(self.decode_inst, "A{}".format(pin_num), name)
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def route_supplies(self):
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def route_supplies(self, bbox=None):
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for inst in self.insts:
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if not inst.mod.name.__contains__("contact"):
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self.copy_layout_pin(inst, "vdd")
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self.copy_layout_pin(inst, "gnd")
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for pin_name in ["vdd", "gnd"]:
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for inst in self.insts:
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self.copy_power_pins(inst, pin_name)
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if not OPTS.route_supplies:
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# Do not route the power supply (leave as must-connect pins)
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return
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elif OPTS.route_supplies == "grid":
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from openram.router import supply_grid_router as router
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else:
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from openram.router import supply_tree_router as router
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rtr=router(layers=self.supply_stack,
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design=self,
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bbox=bbox,
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pin_type=OPTS.supply_pin_type)
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rtr.route()
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if OPTS.supply_pin_type in ["left", "right", "top", "bottom", "ring"]:
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# Find the lowest leftest pin for vdd and gnd
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for pin_name in ["vdd", "gnd"]:
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# Copy the pin shape(s) to rectangles
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for pin in self.get_pins(pin_name):
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self.add_rect(pin.layer,
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pin.ll(),
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pin.width(),
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pin.height())
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# Remove the pin shape(s)
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self.remove_layout_pin(pin_name)
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# Get new pins
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pins = rtr.get_new_pins(pin_name)
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for pin in pins:
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self.add_layout_pin(pin_name,
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pin.layer,
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pin.ll(),
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pin.width(),
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pin.height())
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def route_escape_pins(self, bbox):
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pins_to_route = []
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for bit in range(self.col_bits):
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@ -58,7 +58,7 @@ class rom_base_array(bitcell_base_array):
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self.route_precharge()
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self.add_boundary()
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self.place_rails()
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self.route_supplies()
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self.connect_taps()
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def add_boundary(self):
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@ -86,7 +86,8 @@ class rom_base_array(bitcell_base_array):
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if self.tap_direction == "row":
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self.poly_tap = factory.create(module_type="rom_poly_tap")
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else:
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self.poly_tap = factory.create(module_type="rom_poly_tap", add_tap=True)
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self.poly_tap = factory.create(module_type="rom_poly_tap", add_active_tap=True)
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self.end_poly_tap = factory.create(module_type="rom_poly_tap", place_poly=True)
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self.precharge_array = factory.create(module_type="rom_precharge_array",
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cols=self.column_size,
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strap_spacing=self.strap_spacing,
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@ -109,7 +110,8 @@ class rom_base_array(bitcell_base_array):
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def create_cell_instances(self):
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self.tap_inst = {}
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self.tap_list = []
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self.active_tap_list = []
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self.poly_tap_list = []
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self.cell_inst = {}
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self.cell_list = []
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self.current_row = 0
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@ -129,19 +131,25 @@ class rom_base_array(bitcell_base_array):
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self.cell_inst[row, col] = new_inst
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row_list.append(new_inst)
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name = "tap_r{0}_c{1}".format(row, self.array_col_size)
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new_tap = self.add_inst(name=name, mod=self.poly_tap)
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self.tap_inst[row, self.column_size] = new_tap
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self.tap_list.append(new_tap)
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self.connect_inst([])
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self.create_poly_tap(row, self.column_size)
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# name = "tap_r{0}_c{1}".format(row, self.array_col_size)
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# new_tap = self.add_inst(name=name, mod=self.poly_tap)
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# self.tap_inst[row, self.column_size] = new_tap
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# self.tap_list.append(new_tap)
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# self.connect_inst([])
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self.cell_list.append(row_list)
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def create_poly_tap(self, row, col):
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name = "tap_r{0}_c{1}".format(row, col)
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new_tap = self.add_inst(name=name, mod=self.poly_tap)
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if row == self.row_size and self.tap_direction == "col":
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new_tap = self.add_inst(name=name, mod=self.end_poly_tap)
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else:
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new_tap = self.add_inst(name=name, mod=self.poly_tap)
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self.active_tap_list.append(new_tap)
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self.tap_inst[row, col]=new_tap
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self.tap_list.append(new_tap)
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self.poly_tap_list.append(new_tap)
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self.connect_inst([])
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def create_cell(self, row, col):
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@ -189,15 +197,32 @@ class rom_base_array(bitcell_base_array):
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# Make a flat list too
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self.all_bitline_names = [x for sl in zip(*self.bitline_names) for x in sl]
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def place_rails(self):
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def route_supplies(self):
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via_width = drc("m2_enclose_via1") * 0.5 + drc("minwidth_via1")
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pitch = drc["{0}_to_{0}".format(self.wordline_layer)]
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drain_l = self.cell_list[self.row_size][0].get_pin("D")
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drain_r = self.cell_list[self.row_size][self.column_size - 1].get_pin("D")
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gnd_l = drain_l.center() + vector(-0.5 * self.route_width, pitch + via_width + self.route_pitch)
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gnd_r = drain_r.center() + vector(0.5 * self.route_width, pitch + via_width + self.route_pitch)
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self.add_layout_pin_segment_center(text="gnd", layer=self.bitline_layer, start=gnd_l, end=gnd_r)
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if self.tap_direction == "row":
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self.route_horizontal_pins("gnd", insts=[self], yside="cy")
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self.connect_row_pins(layer=self.wordline_layer, pins=self.gnd_taps, name="gnd")
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self.remove_layout_pin("gnd_tap")
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if self.tap_direction == "col":
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active_tap_pins = [self.active_tap_list[i].get_pin("active_tap") for i in range(len(self.active_tap_list))]
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self.connect_col_pins(layer=self.supply_stack[0], pins=active_tap_pins, name="gnd_tmp")
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for pin in self.get_pins("gnd_tmp"):
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bottom = vector(pin.cx(), pin.by())
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top = vector(pin.cx(), pin.uy())
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self.add_layout_pin_rect_ends(layer=self.supply_stack[0], start=bottom, end=top, name="gnd")
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self.remove_layout_pin("gnd_tmp")
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for i in range(self.column_size):
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drain = self.cell_list[self.row_size][i].get_pin("D")
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gnd_pos = drain.center() + vector(0, pitch + via_width + self.route_pitch)
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self.add_layout_pin_rect_center(text="gnd", layer=self.bitline_layer, offset=gnd_pos)
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self.route_horizontal_pins("gnd", insts=[self], yside="cy")
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self.copy_layout_pin(self.precharge_inst, "vdd")
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@ -231,7 +256,7 @@ class rom_base_array(bitcell_base_array):
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self.tap_inst[row, self.column_size].place(self.strap_pos[row, self.column_size])
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def route_pitch_offsets(self):
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self.gnd_taps = []
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for row in range(0 , self.row_size, self.tap_spacing):
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for col in range(self.column_size):
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@ -270,12 +295,11 @@ class rom_base_array(bitcell_base_array):
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self.add_via_stack_center(offset=tap_pos,
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from_layer=self.active_stack[2],
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to_layer=self.wordline_layer)
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self.add_layout_pin_rect_center("gnd", self.wordline_layer, tap_pos)
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self.gnd_taps.append(self.add_layout_pin_rect_center("gnd_tap", self.wordline_layer, tap_pos))
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def place_precharge(self):
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self.precharge_offset = vector(0, - self.precharge_inst.height - self.zero_cell.nmos.end_to_contact - 2 * drc["nwell_enclose_active"] - 3 * self.m1_pitch)
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self.precharge_inst.place(offset=self.precharge_offset)
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self.copy_layout_pin(self.precharge_inst, "vdd")
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self.copy_layout_pin(self.precharge_inst, "gate", "precharge")
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def place_wordline_contacts(self):
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@ -332,9 +356,6 @@ class rom_base_array(bitcell_base_array):
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self.add_layout_pin_rect_center(text="precharge_r", layer="m1", offset=mid1)
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def connect_taps(self):
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array_pins = [self.tap_list[i].get_pin("poly_tap") for i in range(len(self.tap_list))]
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poly_tap_pins = [self.poly_tap_list[i].get_pin("poly_tap") for i in range(len(self.poly_tap_list))]
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self.connect_row_pins(layer=self.wordline_layer, pins=array_pins, name=None, round=False)
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if self.tap_direction == "col":
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self.route_vertical_pins("active_tap", insts=self.tap_list, layer=self.supply_stack[0], full_width=False)
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self.connect_row_pins(layer=self.wordline_layer, pins=poly_tap_pins)
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@ -165,9 +165,9 @@ class rom_column_mux(pgate):
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# If there is a li layer, include it in the power stack
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self.add_via_stack_center(from_layer=self.active_stack[2],
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to_layer=self.supply_stack[0],
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to_layer=self.pin_layer,
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offset=active_pos)
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self.add_layout_pin_rect_center(text="gnd",
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layer=self.supply_stack[0],
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layer=self.pin_layer,
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offset=active_pos)
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@ -20,7 +20,7 @@ class rom_column_mux_array(design):
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Array of column mux to read the bitlines from ROM, based on the RAM column mux
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"""
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def __init__(self, name, columns, word_size, tap_spacing=4, input_layer="m2", bitline_layer="m1", sel_layer="m2"):
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def __init__(self, name, columns, word_size, tap_spacing=4, input_layer="m1", bitline_layer="m1", sel_layer="m2"):
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super().__init__(name)
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debug.info(1, "Creating {0}".format(self.name))
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self.add_comment("cols: {0} word_size: {1} ".format(columns, word_size))
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@ -31,7 +31,7 @@ class rom_column_mux_array(design):
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self.input_layer = input_layer
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self.tap_spacing = tap_spacing
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self.sel_layer = sel_layer
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self.supply_layer = "m2"
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self.sel_pitch = getattr(self, self.sel_layer + "_pitch")
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self.bitline_layer = bitline_layer
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@ -75,7 +75,7 @@ class rom_column_mux_array(design):
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def add_modules(self):
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self.mux = factory.create(module_type="rom_column_mux", input_layer=self.input_layer, output_layer=self.bitline_layer)
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self.tap = factory.create(module_type="rom_poly_tap", add_tap=True)
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self.tap = factory.create(module_type="rom_poly_tap", add_active_tap=True)
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self.cell = factory.create(module_type="rom_base_cell")
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def setup_layout_constants(self):
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@ -123,7 +123,7 @@ class rom_column_mux_array(design):
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def route_supplies(self):
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self.route_horizontal_pins("gnd", self.insts)
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self.route_horizontal_pins("gnd", self.insts, layer=self.supply_layer)
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def add_routing(self):
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self.add_horizontal_input_rail()
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@ -101,10 +101,10 @@ class rom_control_logic(design):
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self.copy_layout_pin(self.buf_inst, "Z", "clk_out")
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self.copy_layout_pin(self.driver_inst, "Z", "prechrg")
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self.copy_layout_pin(self.nand_inst, "A", "CS")
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self.copy_layout_pin(self.buf_inst, "gnd")
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self.copy_layout_pin(self.driver_inst, "vdd")
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self.copy_layout_pin(self.buf_inst, "vdd")
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self.copy_power_pin(self.buf_inst.get_pin("gnd"), directions="nonpref")
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self.copy_power_pin(self.driver_inst.get_pin("gnd"), directions="nonpref")
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self.copy_power_pin(self.buf_inst.get_pin("vdd"), directions="nonpref")
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clk = self.buf_inst.get_pin("Z")
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nand_B = self.nand_inst.get_pin("B")
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@ -13,11 +13,15 @@ from openram.tech import drc
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class rom_poly_tap(design):
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def __init__(self, name="", cell_name=None, tx_type="nmos", strap_layer="m2", add_tap=False):
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def __init__(self, name="", cell_name=None, tx_type="nmos", strap_layer="m2", add_active_tap=False, place_poly=None):
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super().__init__(name, cell_name)
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self.strap_layer=strap_layer
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self.tx_type = tx_type
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self.add_tap = add_tap
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self.add_tap = add_active_tap
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if place_poly is None:
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||||
self.place_poly = add_active_tap
|
||||
else:
|
||||
self.place_poly = place_poly
|
||||
self.pitch_offset = 0
|
||||
self.create_netlist()
|
||||
self.create_layout()
|
||||
|
|
@ -32,7 +36,7 @@ class rom_poly_tap(design):
|
|||
|
||||
self.place_via()
|
||||
self.add_boundary()
|
||||
if self.add_tap:
|
||||
if self.add_tap or self.place_poly:
|
||||
self.place_active_tap()
|
||||
self.extend_poly()
|
||||
|
||||
|
|
@ -47,14 +51,6 @@ class rom_poly_tap(design):
|
|||
|
||||
contact_width = self.poly_contact.width
|
||||
|
||||
# DRC rule here is hard coded since licon.9 isnt included in skywater130 tech file
|
||||
|
||||
# poly contact spacing to P-diffusion < 0.235um (licon.9 + psdm.5a)
|
||||
# if OPTS.tech_name == "sky130":
|
||||
# self.contact_x_offset = 0.235 - (contact_width - self.pmos.contact_width) * 0.5 - self.poly_extend_active
|
||||
# else:
|
||||
# assert(False)
|
||||
|
||||
contact_y = self.dummy.cell_inst.width * 0.5 - 0.5 * self.contact_width - self.active_enclose_contact
|
||||
|
||||
self.contact_x_offset = 0
|
||||
|
|
@ -91,13 +87,10 @@ class rom_poly_tap(design):
|
|||
tap_edge = tap_x + 0.5 * self.active_contact.height
|
||||
self.pitch_offset += (self.active_space * 2) - (tap_edge - active_edge) + self.contact_x_offset
|
||||
|
||||
if self.tx_type == "nmos":
|
||||
if self.tx_type == "nmos" and self.add_tap:
|
||||
self.add_via_center(layers=self.active_stack,
|
||||
offset=contact_pos,
|
||||
implant_type="p",
|
||||
well_type="p",
|
||||
directions="nonpref")
|
||||
self.add_power_pin(name="gnd",
|
||||
loc=contact_pos,
|
||||
start_layer=self.active_stack[2])
|
||||
self.add_layout_pin_rect_center("active_tap", self.supply_stack[0], contact_pos)
|
||||
self.add_layout_pin_rect_center("active_tap", self.active_stack[2], contact_pos)
|
||||
|
|
@ -83,7 +83,7 @@ class rom_precharge_array(design):
|
|||
# For layout constants
|
||||
self.dummy = factory.create(module_type="rom_base_cell")
|
||||
|
||||
self.poly_tap = factory.create(module_type="rom_poly_tap", tx_type="pmos", add_tap=(self.tap_direction == "col"))
|
||||
self.poly_tap = factory.create(module_type="rom_poly_tap", tx_type="pmos", add_active_tap=(self.tap_direction == "col"))
|
||||
|
||||
def add_pins(self):
|
||||
for col in range(self.cols):
|
||||
|
|
|
|||
|
|
@ -49,11 +49,13 @@ class rom_wordline_driver_array(design):
|
|||
self.route_layer = "m1"
|
||||
self.place_drivers()
|
||||
self.route_layout()
|
||||
self.route_supplies()
|
||||
|
||||
if self.tap_spacing != 0:
|
||||
self.place_taps()
|
||||
self.route_supplies()
|
||||
self.add_boundary()
|
||||
|
||||
|
||||
def add_pins(self):
|
||||
# inputs to wordline_driver.
|
||||
for i in range(self.rows):
|
||||
|
|
@ -66,7 +68,7 @@ class rom_wordline_driver_array(design):
|
|||
|
||||
def add_modules(self):
|
||||
b = factory.create(module_type="rom_base_cell")
|
||||
self.tap = factory.create(module_type="rom_poly_tap", add_tap = True)
|
||||
self.tap = factory.create(module_type="rom_poly_tap", add_active_tap = True)
|
||||
|
||||
if self.invert_outputs:
|
||||
self.wl_driver = factory.create(module_type="pinv_dec",
|
||||
|
|
@ -86,13 +88,41 @@ class rom_wordline_driver_array(design):
|
|||
Add a pin for each row of vdd/gnd which
|
||||
are must-connects next level up.
|
||||
"""
|
||||
|
||||
if layer_props.wordline_driver.vertical_supply:
|
||||
self.route_vertical_pins("vdd", [self], layer=self.supply_layer)
|
||||
self.route_vertical_pins("gnd", [self], layer=self.supply_layer)
|
||||
# self.route_vertical_pins("vdd", self.wld_inst, xside="cx", layer=self.supply_layer)
|
||||
# self.route_vertical_pins("gnd", self.wld_inst, xside="cx", layer=self.supply_layer)
|
||||
if not self.invert_outputs:
|
||||
vdd_pins = [pin for inst in self.wld_inst for pin in inst.get_pins("vdd")]
|
||||
gnd_pins = [pin for inst in self.wld_inst for pin in inst.get_pins("gnd")]
|
||||
else:
|
||||
self.route_vertical_pins("vdd", self.wld_inst, xside="rx",)
|
||||
self.route_vertical_pins("gnd", self.wld_inst, xside="lx",)
|
||||
vdd_pins = [inst.get_pin("vdd") for inst in self.wld_inst]
|
||||
gnd_pins = [inst.get_pin("gnd") for inst in self.wld_inst]
|
||||
if self.tap_spacing != 0:
|
||||
vdd_pins = vdd_pins + self.vdd_taps
|
||||
gnd_pins = gnd_pins + self.gnd_taps
|
||||
|
||||
supply_width = drc["minwidth_{}".format(self.supply_layer)]
|
||||
|
||||
# Route together all internal supply pins
|
||||
self.connect_col_pins(layer=self.supply_layer, pins=vdd_pins, name="vdd_tmp")
|
||||
self.connect_col_pins(layer=self.supply_layer, pins=gnd_pins, name="gnd_tmp")
|
||||
self.remove_layout_pin("gnd_tap")
|
||||
self.remove_layout_pin("vdd_tap")
|
||||
|
||||
# Place the top level supply pins on the edge of the module
|
||||
for pin in self.get_pins("gnd_tmp"):
|
||||
bottom = vector(pin.cx(), pin.by() - 0.5 * supply_width)
|
||||
top = vector(pin.cx(), pin.uy() + 0.5 * supply_width)
|
||||
self.add_layout_pin_rect_ends(layer=self.supply_layer, start=bottom, end=top, name="gnd")
|
||||
|
||||
for pin in self.get_pins("vdd_tmp"):
|
||||
bottom = vector(pin.cx(), pin.by() - 0.5 * supply_width)
|
||||
top = vector(pin.cx(), pin.uy() + 0.5 * supply_width)
|
||||
self.add_layout_pin_rect_ends(layer=self.supply_layer, start=bottom, end=top, name="vdd")
|
||||
|
||||
|
||||
self.remove_layout_pin("gnd_tmp")
|
||||
self.remove_layout_pin("vdd_tmp")
|
||||
|
||||
|
||||
def create_drivers(self):
|
||||
self.wld_inst = []
|
||||
|
|
@ -125,8 +155,7 @@ class rom_wordline_driver_array(design):
|
|||
else:
|
||||
row_num = row
|
||||
inst = self.wld_inst[row_num]
|
||||
self.copy_layout_pin(inst, "vdd")
|
||||
self.copy_layout_pin(inst, "gnd")
|
||||
|
||||
|
||||
self.copy_layout_pin(inst, "A", "in_{0}".format(row))
|
||||
|
||||
|
|
@ -151,7 +180,8 @@ class rom_wordline_driver_array(design):
|
|||
self.add_layout_pin_rect_center(text="out_{}".format(row), layer=self.route_layer, offset=end - vector(0, 0.5 * route_width))
|
||||
|
||||
def place_taps(self):
|
||||
|
||||
self.vdd_taps = []
|
||||
self.gnd_taps = []
|
||||
for wl in range(0 , self.rows, self.tap_spacing):
|
||||
driver = self.wld_inst[wl]
|
||||
|
||||
|
|
@ -176,6 +206,7 @@ class rom_wordline_driver_array(design):
|
|||
self.place_tap(contact_pos, "p")
|
||||
|
||||
def place_tap(self, offset, well_type):
|
||||
|
||||
self.add_via_center(layers=self.active_stack,
|
||||
offset=offset,
|
||||
implant_type=well_type,
|
||||
|
|
@ -185,7 +216,8 @@ class rom_wordline_driver_array(design):
|
|||
from_layer=self.active_stack[2],
|
||||
to_layer=self.supply_layer)
|
||||
if well_type == "p":
|
||||
pin = "gnd"
|
||||
pin = "gnd_tap"
|
||||
self.gnd_taps.append(self.add_layout_pin_rect_center(text=pin, layer=self.supply_layer, offset=offset))
|
||||
else:
|
||||
pin = "vdd"
|
||||
self.add_layout_pin_rect_center(text=pin, layer=self.supply_layer, offset=offset)
|
||||
pin = "vdd_tap"
|
||||
self.vdd_taps.append(self.add_layout_pin_rect_center(text=pin, layer=self.supply_layer, offset=offset))
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
tech_name = "sky130"
|
||||
nominal_corner_only = True
|
||||
|
||||
#route_supplies = "ring"
|
||||
#check_lvsdrc = True
|
||||
check_lvsdrc = False
|
||||
route_supplies = "ring"
|
||||
check_lvsdrc = True
|
||||
# check_lvsdrc = False
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue