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https://github.com/VLSIDA/OpenRAM.git
synced 2026-08-30 09:58:33 +02:00
rom base passing tests with top level routing
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@@ -49,11 +49,13 @@ class rom_wordline_driver_array(design):
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self.route_layer = "m1"
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self.place_drivers()
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self.route_layout()
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self.route_supplies()
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if self.tap_spacing != 0:
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self.place_taps()
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self.route_supplies()
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self.add_boundary()
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def add_pins(self):
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# inputs to wordline_driver.
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for i in range(self.rows):
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@@ -66,7 +68,7 @@ class rom_wordline_driver_array(design):
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def add_modules(self):
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b = factory.create(module_type="rom_base_cell")
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self.tap = factory.create(module_type="rom_poly_tap", add_tap = True)
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self.tap = factory.create(module_type="rom_poly_tap", add_active_tap = True)
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if self.invert_outputs:
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self.wl_driver = factory.create(module_type="pinv_dec",
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@@ -86,13 +88,41 @@ class rom_wordline_driver_array(design):
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Add a pin for each row of vdd/gnd which
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are must-connects next level up.
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"""
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if layer_props.wordline_driver.vertical_supply:
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self.route_vertical_pins("vdd", [self], layer=self.supply_layer)
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self.route_vertical_pins("gnd", [self], layer=self.supply_layer)
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# self.route_vertical_pins("vdd", self.wld_inst, xside="cx", layer=self.supply_layer)
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# self.route_vertical_pins("gnd", self.wld_inst, xside="cx", layer=self.supply_layer)
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if not self.invert_outputs:
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vdd_pins = [pin for inst in self.wld_inst for pin in inst.get_pins("vdd")]
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gnd_pins = [pin for inst in self.wld_inst for pin in inst.get_pins("gnd")]
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else:
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self.route_vertical_pins("vdd", self.wld_inst, xside="rx",)
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self.route_vertical_pins("gnd", self.wld_inst, xside="lx",)
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vdd_pins = [inst.get_pin("vdd") for inst in self.wld_inst]
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gnd_pins = [inst.get_pin("gnd") for inst in self.wld_inst]
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if self.tap_spacing != 0:
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vdd_pins = vdd_pins + self.vdd_taps
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gnd_pins = gnd_pins + self.gnd_taps
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supply_width = drc["minwidth_{}".format(self.supply_layer)]
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# Route together all internal supply pins
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self.connect_col_pins(layer=self.supply_layer, pins=vdd_pins, name="vdd_tmp")
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self.connect_col_pins(layer=self.supply_layer, pins=gnd_pins, name="gnd_tmp")
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self.remove_layout_pin("gnd_tap")
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self.remove_layout_pin("vdd_tap")
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# Place the top level supply pins on the edge of the module
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for pin in self.get_pins("gnd_tmp"):
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bottom = vector(pin.cx(), pin.by() - 0.5 * supply_width)
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top = vector(pin.cx(), pin.uy() + 0.5 * supply_width)
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self.add_layout_pin_rect_ends(layer=self.supply_layer, start=bottom, end=top, name="gnd")
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for pin in self.get_pins("vdd_tmp"):
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bottom = vector(pin.cx(), pin.by() - 0.5 * supply_width)
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top = vector(pin.cx(), pin.uy() + 0.5 * supply_width)
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self.add_layout_pin_rect_ends(layer=self.supply_layer, start=bottom, end=top, name="vdd")
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self.remove_layout_pin("gnd_tmp")
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self.remove_layout_pin("vdd_tmp")
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def create_drivers(self):
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self.wld_inst = []
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@@ -125,8 +155,7 @@ class rom_wordline_driver_array(design):
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else:
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row_num = row
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inst = self.wld_inst[row_num]
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self.copy_layout_pin(inst, "vdd")
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self.copy_layout_pin(inst, "gnd")
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self.copy_layout_pin(inst, "A", "in_{0}".format(row))
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@@ -151,7 +180,8 @@ class rom_wordline_driver_array(design):
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self.add_layout_pin_rect_center(text="out_{}".format(row), layer=self.route_layer, offset=end - vector(0, 0.5 * route_width))
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def place_taps(self):
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self.vdd_taps = []
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self.gnd_taps = []
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for wl in range(0 , self.rows, self.tap_spacing):
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driver = self.wld_inst[wl]
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@@ -176,6 +206,7 @@ class rom_wordline_driver_array(design):
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self.place_tap(contact_pos, "p")
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def place_tap(self, offset, well_type):
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self.add_via_center(layers=self.active_stack,
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offset=offset,
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implant_type=well_type,
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@@ -185,7 +216,8 @@ class rom_wordline_driver_array(design):
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from_layer=self.active_stack[2],
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to_layer=self.supply_layer)
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if well_type == "p":
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pin = "gnd"
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pin = "gnd_tap"
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self.gnd_taps.append(self.add_layout_pin_rect_center(text=pin, layer=self.supply_layer, offset=offset))
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else:
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pin = "vdd"
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self.add_layout_pin_rect_center(text=pin, layer=self.supply_layer, offset=offset)
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pin = "vdd_tap"
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self.vdd_taps.append(self.add_layout_pin_rect_center(text=pin, layer=self.supply_layer, offset=offset))
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