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rom base passing tests with top level routing
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@@ -107,4 +107,16 @@ class rom_address_control_array(design):
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def route_sources(self):
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self.route_horizontal_pins("vdd", insts=self.buf_insts, layer=self.route_layer)
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self.route_horizontal_pins("gnd", insts=self.buf_insts, layer=self.route_layer)
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self.route_horizontal_pins("gnd", insts=self.buf_insts, layer=self.route_layer)
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tmp_pins = []
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for pin in self.get_pins("vdd"):
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edge = vector(pin.lx() + 0.5 * self.route_width, pin.cy())
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tmp_pins.append(self.add_layout_pin_rect_center("vdd_edge", layer=self.route_layer, offset=edge))
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self.copy_layout_pin_shapes("vdd")
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self.remove_layout_pin("vdd")
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for pin in tmp_pins:
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print("copying pin")
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self.copy_layout_pin(self, "vdd_edge", "vdd")
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self.remove_layout_pin("vdd_edge")
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