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rom base passing tests with top level routing

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This commit is contained in:
Jacob Walker
2023-03-30 11:30:50 -07:00
parent 7c453e80be
commit fef9902c45
11 changed files with 176 additions and 83 deletions
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compiler/base/hierarchy_layout.py
+2 -2
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@@ -1897,7 +1897,7 @@ class layout():
elif add_vias:
self.copy_power_pin(pin, new_name=new_name)
def add_io_pin(self, instance, pin_name, new_name, start_layer=None):
def add_io_pin(self, instance, pin_name, new_name, start_layer=None, directions=None):
"""
Add a signle input or output pin up to metal 3.
"""
@@ -1907,7 +1907,7 @@ class layout():
start_layer = pin.layer
# Just use the power pin function for now to save code
self.add_power_pin(new_name, pin.center(), start_layer=start_layer)
self.add_power_pin(new_name, pin.center(), start_layer=start_layer, directions=directions)
def add_power_pin(self, name, loc, directions=None, start_layer="m1"):
# Hack for min area