mirror of https://github.com/VLSIDA/OpenRAM.git
Fix wrong power layer for min area constraint
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@ -1398,7 +1398,7 @@ class layout():
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def add_power_pin(self, name, loc, directions=None, start_layer="m1"):
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def add_power_pin(self, name, loc, directions=None, start_layer="m1"):
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# Hack for min area
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# Hack for min area
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if OPTS.tech_name == "sky130":
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if OPTS.tech_name == "sky130":
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min_area = drc["minarea_{}".format(self.pwr_grid_layers[2])]
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min_area = drc["minarea_{}".format(self.pwr_grid_layers[1])]
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width = round_to_grid(sqrt(min_area))
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width = round_to_grid(sqrt(min_area))
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height = round_to_grid(min_area / width)
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height = round_to_grid(min_area / width)
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else:
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else:
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