luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Move info messages about modes to better locations.

This commit is contained in:
Matt Guthaus 2018-01-05 08:32:23 -08:00
parent 4885616bec
commit fd748b4fe4
2 changed files with 10 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
compiler/characterizer/__init__.py
View File

@ -10,9 +10,7 @@ debug.info(2,"Initializing characterizer...")
spice_exe = "" spice_exe = ""
if OPTS.analytical_delay: if not OPTS.analytical_delay:
debug.info(1,"Using analytical delay models (no characterization)")
else:
if OPTS.spice_name != "": if OPTS.spice_name != "":
spice_exe=find_exe(OPTS.spice_name) spice_exe=find_exe(OPTS.spice_name)
if spice_exe=="": if spice_exe=="":

20
compiler/openram.py
View File

@ -64,16 +64,6 @@ print("Output files are " + OPTS.output_name + ".(sp|gds|v|lib|lef)")
print("Technology: {0}".format(OPTS.tech_name)) print("Technology: {0}".format(OPTS.tech_name))
print("Word size: {0}\nWords: {1}\nBanks: {2}".format(word_size,num_words,num_banks)) print("Word size: {0}\nWords: {1}\nBanks: {2}".format(word_size,num_words,num_banks))
if not OPTS.check_lvsdrc:
print("DRC/LVS/PEX checking is disabled.")
if OPTS.analytical_delay:
print("Using analytical delay models (no characterization)")
else:
print("Performing simulation-based characterization with {}".format(OPTS.spice_name))
if OPTS.trim_netlist:
print("Trimming netlist to speed up characterization (sacrificing some accuracy).")
# only start importing modules after we have the config file # only start importing modules after we have the config file
import verify import verify
import sram import sram
@ -81,7 +71,8 @@ import sram
start_time = datetime.datetime.now() start_time = datetime.datetime.now()
last_time = start_time last_time = start_time
print_time("Start",datetime.datetime.now()) print_time("Start",datetime.datetime.now())
if not OPTS.check_lvsdrc:
print("DRC/LVS/PEX checking is disabled.")
# import SRAM test generation # import SRAM test generation
s = sram.sram(word_size=word_size, s = sram.sram(word_size=word_size,
num_words=num_words, num_words=num_words,
@ -110,6 +101,13 @@ if OPTS.use_pex:
from characterizer import lib from characterizer import lib
libname = OPTS.output_path + s.name + ".lib" libname = OPTS.output_path + s.name + ".lib"
print("LIB: Writing to {0}".format(libname)) print("LIB: Writing to {0}".format(libname))
if OPTS.analytical_delay:
print("Using analytical delay models (no characterization)")
else:
if OPTS.spice_name!="":
print("Performing simulation-based characterization with {}".format(OPTS.spice_name))
if OPTS.trim_netlist:
print("Trimming netlist to speed up characterization.")
lib.lib(libname,s,sram_file) lib.lib(libname,s,sram_file)
last_time=print_time("Characterization", datetime.datetime.now(), last_time) last_time=print_time("Characterization", datetime.datetime.now(), last_time)