mirror of https://github.com/VLSIDA/OpenRAM.git
Add tech specific skip tests for making new techs.
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parent
580b0601b5
commit
fd49d3ed6a
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@ -25,14 +25,14 @@ scn4m_subm:
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- .coverage.*
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- .coverage.*
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expire_in: 1 week
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expire_in: 1 week
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# s8:
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s8:
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# stage: test
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stage: test
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# script:
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script:
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# - coverage run -p $OPENRAM_HOME/tests/regress.py -t s8
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- coverage run -p $OPENRAM_HOME/tests/regress.py -t s8
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# artifacts:
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artifacts:
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# paths:
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paths:
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# - .coverage.*
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- .coverage.*
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# expire_in: 1 week
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expire_in: 1 week
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coverage:
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coverage:
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stage: coverage
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stage: coverage
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@ -12,6 +12,7 @@ import unittest
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import sys,os
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import sys,os
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sys.path.append(os.getenv("OPENRAM_HOME"))
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sys.path.append(os.getenv("OPENRAM_HOME"))
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import globals
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import globals
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import debug
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(OPTS, args) = globals.parse_args()
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(OPTS, args) = globals.parse_args()
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del sys.argv[1:]
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del sys.argv[1:]
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@ -22,14 +23,25 @@ header(__file__, OPTS.tech_name)
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# get a list of all files in the tests directory
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# get a list of all files in the tests directory
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files = os.listdir(sys.path[0])
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files = os.listdir(sys.path[0])
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# load a file with all tests to skip in a given technology
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# since tech_name is dynamically loaded, we can't use @skip directives
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try:
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skip_file = open("skip_tests_{}.txt".format(OPTS.tech_name), "r")
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skip_tests = skip_file.read().splitlines()
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for st in skip_tests:
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debug.warning("Skipping: " + st)
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except FileNotFoundError:
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skip_tests = []
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# assume any file that ends in "test.py" in it is a regression test
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# assume any file that ends in "test.py" in it is a regression test
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nametest = re.compile("test\.py$", re.IGNORECASE)
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nametest = re.compile("test\.py$", re.IGNORECASE)
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tests = list(filter(nametest.search, files))
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all_tests = list(filter(nametest.search, files))
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tests.sort()
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filtered_tests = list(filter(lambda i: i not in skip_tests, all_tests))
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filtered_tests.sort()
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# import all of the modules
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# import all of the modules
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filenameToModuleName = lambda f: os.path.splitext(f)[0]
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filenameToModuleName = lambda f: os.path.splitext(f)[0]
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moduleNames = map(filenameToModuleName, tests)
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moduleNames = map(filenameToModuleName, filtered_tests)
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modules = map(__import__, moduleNames)
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modules = map(__import__, moduleNames)
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suite = unittest.TestSuite()
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suite = unittest.TestSuite()
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load = unittest.defaultTestLoader.loadTestsFromModule
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load = unittest.defaultTestLoader.loadTestsFromModule
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@ -0,0 +1,56 @@
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04_dummy_pbitcell_test.py
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04_pbitcell_test.py
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04_precharge_pbitcell_test.py
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04_replica_pbitcell_test.py
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04_single_level_column_mux_pbitcell_test.py
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05_pbitcell_array_test.py
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06_hierarchical_decoder_pbitcell_test.py
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06_hierarchical_predecode2x4_pbitcell_test.py
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06_hierarchical_predecode3x8_pbitcell_test.py
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07_single_level_column_mux_array_pbitcell_test.py
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08_wordline_driver_array_pbitcell_test.py
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09_sense_amp_array_test_pbitcell.py
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10_write_driver_array_pbitcell_test.py
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10_write_driver_array_wmask_pbitcell_test.py
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10_write_mask_and_array_pbitcell_test.py
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14_replica_pbitcell_array_test.py
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19_bank_select_pbitcell_test.py
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05_bitcell_1rw_1r_array_test.py
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05_bitcell_array_test.py
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05_dummy_array_test.py
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05_pbitcell_array_test.py
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06_hierarchical_decoder_pbitcell_test.py
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06_hierarchical_decoder_test.py
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06_hierarchical_predecode2x4_pbitcell_test.py
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06_hierarchical_predecode2x4_test.py
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06_hierarchical_predecode3x8_pbitcell_test.py
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06_hierarchical_predecode3x8_test.py
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06_hierarchical_predecode4x16_test.py
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04_dummy_pbitcell_test.py
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04_pbitcell_test.py
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04_precharge_pbitcell_test.py
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04_replica_pbitcell_test.py
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04_single_level_column_mux_pbitcell_test.py
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05_bitcell_1rw_1r_array_test.py
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05_bitcell_array_test.py
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05_dummy_array_test.py
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05_pbitcell_array_test.py
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05_pbitcell_array_test.py
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06_hierarchical_decoder_pbitcell_test.py
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06_hierarchical_decoder_pbitcell_test.py
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06_hierarchical_decoder_test.py
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06_hierarchical_predecode2x4_pbitcell_test.py
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06_hierarchical_predecode2x4_pbitcell_test.py
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06_hierarchical_predecode2x4_test.py
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06_hierarchical_predecode3x8_pbitcell_test.py
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06_hierarchical_predecode3x8_pbitcell_test.py
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06_hierarchical_predecode3x8_test.py
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06_hierarchical_predecode4x16_test.py
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07_single_level_column_mux_array_pbitcell_test.py
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08_wordline_driver_array_pbitcell_test.py
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09_sense_amp_array_test_pbitcell.py
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10_write_driver_array_pbitcell_test.py
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10_write_driver_array_wmask_pbitcell_test.py
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10_write_mask_and_array_pbitcell_test.py
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14_replica_pbitcell_array_test.py
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19_bank_select_pbitcell_test.py
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