mirror of https://github.com/VLSIDA/OpenRAM.git
Default zom is None not negative.
This commit is contained in:
parent
9d9f0fddf0
commit
fd118c62e5
|
|
@ -498,7 +498,7 @@ class layout():
|
||||||
offset=offset + vector(0.5 * width,
|
offset=offset + vector(0.5 * width,
|
||||||
0.5 * height))
|
0.5 * height))
|
||||||
|
|
||||||
def add_label(self, text, layer, offset=[0, 0], zoom=-1):
|
def add_label(self, text, layer, offset=[0, 0], zoom=None):
|
||||||
"""Adds a text label on the given layer,offset, and zoom level"""
|
"""Adds a text label on the given layer,offset, and zoom level"""
|
||||||
debug.info(5, "add label " + str(text) + " " + layer + " " + str(offset))
|
debug.info(5, "add label " + str(text) + " " + layer + " " + str(offset))
|
||||||
lpp = techlayer[layer]
|
lpp = techlayer[layer]
|
||||||
|
|
|
||||||
|
|
@ -3,7 +3,6 @@
|
||||||
04_precharge_pbitcell_test.py
|
04_precharge_pbitcell_test.py
|
||||||
04_replica_pbitcell_test.py
|
04_replica_pbitcell_test.py
|
||||||
04_column_mux_pbitcell_test.py
|
04_column_mux_pbitcell_test.py
|
||||||
05_bitcell_1rw_1r_array_test.py
|
|
||||||
05_bitcell_array_test.py
|
05_bitcell_array_test.py
|
||||||
05_dummy_array_test.py
|
05_dummy_array_test.py
|
||||||
05_pbitcell_array_test.py
|
05_pbitcell_array_test.py
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue