mirror of https://github.com/VLSIDA/OpenRAM.git
Code formatting
This commit is contained in:
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05ab45f39b
commit
fcfb9391f6
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@ -605,8 +605,8 @@ class delay(simulation):
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return net
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return net
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original_net = net
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original_net = net
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net = net[len(prefix):]
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net = net[len(prefix):]
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net = net.replace(".", "_").replace("[", "\[").replace("]", "\]")
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net = net.replace(".", "_").replace("[", r"\[").replace("]", r"\]")
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for pattern in ["\sN_{}_[MXmx]\S+_[gsd]".format(net), net]:
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for pattern in [r"\sN_{}_[MXmx]\S+_[gsd]".format(net), net]:
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try:
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try:
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match = check_output(["grep", "-m1", "-o", "-iE", pattern, self.sp_file])
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match = check_output(["grep", "-m1", "-o", "-iE", pattern, self.sp_file])
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return prefix + match.decode().strip()
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return prefix + match.decode().strip()
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@ -616,8 +616,8 @@ class delay(simulation):
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def load_all_measure_nets(self):
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def load_all_measure_nets(self):
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measurement_nets = set()
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measurement_nets = set()
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for port, meas in zip(self.targ_read_ports * len(self.read_meas_lists) +
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for port, meas in zip(self.targ_read_ports * len(self.read_meas_lists)
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self.targ_write_ports * len(self.write_meas_lists),
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+ self.targ_write_ports * len(self.write_meas_lists),
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self.read_meas_lists + self.write_meas_lists):
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self.read_meas_lists + self.write_meas_lists):
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for measurement in meas:
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for measurement in meas:
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visited = getattr(measurement, 'pex_visited', False)
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visited = getattr(measurement, 'pex_visited', False)
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@ -1168,7 +1168,7 @@ class delay(simulation):
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# 4) At the minimum period, measure the delay, slew and power for all slew/load pairs.
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# 4) At the minimum period, measure the delay, slew and power for all slew/load pairs.
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self.period = min_period
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self.period = min_period
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char_port_data = self.simulate_loads_and_slews(load_slews, leakage_offset)
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char_port_data = self.simulate_loads_and_slews(load_slews, leakage_offset)
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if OPTS.use_specified_load_slew != None and len(load_slews) > 1:
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if OPTS.use_specified_load_slew is not None and len(load_slews) > 1:
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debug.warning("Path delay lists not correctly generated for characterizations of more than 1 load,slew")
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debug.warning("Path delay lists not correctly generated for characterizations of more than 1 load,slew")
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# Get and save the path delays
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# Get and save the path delays
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bl_names, bl_delays, sen_names, sen_delays = self.get_delay_lists(self.path_delays)
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bl_names, bl_delays, sen_names, sen_delays = self.get_delay_lists(self.path_delays)
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@ -1194,7 +1194,6 @@ class delay(simulation):
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"""Simulate all specified output loads and input slews pairs of all ports"""
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"""Simulate all specified output loads and input slews pairs of all ports"""
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measure_data = self.get_empty_measure_data_dict()
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measure_data = self.get_empty_measure_data_dict()
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path_dict = {}
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# Set the target simulation ports to all available ports. This make sims slower but failed sims exit anyways.
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# Set the target simulation ports to all available ports. This make sims slower but failed sims exit anyways.
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self.targ_read_ports = self.read_ports
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self.targ_read_ports = self.read_ports
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self.targ_write_ports = self.write_ports
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self.targ_write_ports = self.write_ports
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@ -1352,9 +1351,9 @@ class delay(simulation):
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# Get any available read/write port in case only a single write or read ports is being characterized.
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# Get any available read/write port in case only a single write or read ports is being characterized.
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cur_read_port = self.get_available_port(get_read_port=True)
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cur_read_port = self.get_available_port(get_read_port=True)
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cur_write_port = self.get_available_port(get_read_port=False)
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cur_write_port = self.get_available_port(get_read_port=False)
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debug.check(cur_read_port != None,
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debug.check(cur_read_port is not None,
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"Characterizer requires at least 1 read port")
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"Characterizer requires at least 1 read port")
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debug.check(cur_write_port != None,
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debug.check(cur_write_port is not None,
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"Characterizer requires at least 1 write port")
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"Characterizer requires at least 1 write port")
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# Create test cycles for specified target ports.
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# Create test cycles for specified target ports.
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@ -146,7 +146,6 @@ class functional(simulation):
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comment = self.gen_cycle_comment("noop", "0" * self.word_size, "0" * self.addr_size, "0" * self.num_wmasks, 0, self.t_current)
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comment = self.gen_cycle_comment("noop", "0" * self.word_size, "0" * self.addr_size, "0" * self.num_wmasks, 0, self.t_current)
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self.add_noop_all_ports(comment)
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self.add_noop_all_ports(comment)
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# 1. Write all the write ports 2x to seed a bunch of locations.
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# 1. Write all the write ports 2x to seed a bunch of locations.
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for i in range(3):
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for i in range(3):
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for port in self.write_ports:
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for port in self.write_ports:
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@ -11,6 +11,7 @@ from abc import ABC, abstractmethod
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from .stimuli import *
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from .stimuli import *
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from .charutils import *
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from .charutils import *
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class spice_measurement(ABC):
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class spice_measurement(ABC):
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"""Base class for spice stimulus measurements."""
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"""Base class for spice stimulus measurements."""
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def __init__(self, measure_name, measure_scale=None, has_port=True):
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def __init__(self, measure_name, measure_scale=None, has_port=True):
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@ -21,6 +22,7 @@ class spice_measurement(ABC):
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# Some meta values used externally. variables are added here for consistency accross the objects
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# Some meta values used externally. variables are added here for consistency accross the objects
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self.meta_str = None
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self.meta_str = None
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self.meta_add_delay = False
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self.meta_add_delay = False
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@abstractmethod
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@abstractmethod
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def get_measure_function(self):
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def get_measure_function(self):
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return None
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return None
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@ -31,26 +33,26 @@ class spice_measurement(ABC):
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def write_measure(self, stim_obj, input_tuple):
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def write_measure(self, stim_obj, input_tuple):
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measure_func = self.get_measure_function()
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measure_func = self.get_measure_function()
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if measure_func == None:
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if measure_func is None:
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debug.error("Did not set measure function", 1)
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debug.error("Did not set measure function", 1)
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measure_vals = self.get_measure_values(*input_tuple)
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measure_vals = self.get_measure_values(*input_tuple)
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measure_func(stim_obj, *measure_vals)
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measure_func(stim_obj, *measure_vals)
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def retrieve_measure(self, port=None):
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def retrieve_measure(self, port=None):
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self.port_error_check(port)
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self.port_error_check(port)
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if port != None:
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if port is not None:
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value = parse_spice_list("timing", "{0}{1}".format(self.name.lower(), port))
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value = parse_spice_list("timing", "{0}{1}".format(self.name.lower(), port))
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else:
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else:
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value = parse_spice_list("timing", "{0}".format(self.name.lower()))
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value = parse_spice_list("timing", "{0}".format(self.name.lower()))
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if type(value)!=float or self.measure_scale == None:
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if type(value)!=float or self.measure_scale is None:
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return value
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return value
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else:
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else:
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return value * self.measure_scale
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return value * self.measure_scale
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def port_error_check(self, port):
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def port_error_check(self, port):
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if self.has_port and port == None:
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if self.has_port and port is None:
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debug.error("Cannot retrieve measurement, port input was expected.", 1)
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debug.error("Cannot retrieve measurement, port input was expected.", 1)
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elif not self.has_port and port != None:
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elif not self.has_port and port is not None:
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debug.error("Unexpected port input received during measure retrieval.", 1)
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debug.error("Unexpected port input received during measure retrieval.", 1)
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@ -90,7 +92,7 @@ class delay_measure(spice_measurement):
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trig_val = self.trig_val_of_vdd * vdd_voltage
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trig_val = self.trig_val_of_vdd * vdd_voltage
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targ_val = self.targ_val_of_vdd * vdd_voltage
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targ_val = self.targ_val_of_vdd * vdd_voltage
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if port != None:
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if port is not None:
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# For dictionary indexing reasons, the name is formatted differently than the signals
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# For dictionary indexing reasons, the name is formatted differently than the signals
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meas_name = "{}{}".format(self.name, port)
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meas_name = "{}{}".format(self.name, port)
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trig_name = self.trig_name_no_port.format(port)
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trig_name = self.trig_name_no_port.format(port)
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@ -145,7 +147,7 @@ class power_measure(spice_measurement):
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def get_measure_values(self, t_initial, t_final, port=None):
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def get_measure_values(self, t_initial, t_final, port=None):
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"""Constructs inputs to stimulus measurement function. Variant values are inputs here."""
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"""Constructs inputs to stimulus measurement function. Variant values are inputs here."""
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self.port_error_check(port)
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self.port_error_check(port)
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if port != None:
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if port is not None:
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meas_name = "{}{}".format(self.name, port)
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meas_name = "{}{}".format(self.name, port)
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else:
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else:
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meas_name = self.name
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meas_name = self.name
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@ -172,7 +174,7 @@ class voltage_when_measure(spice_measurement):
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def get_measure_values(self, trig_td, vdd_voltage, port=None):
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def get_measure_values(self, trig_td, vdd_voltage, port=None):
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"""Constructs inputs to stimulus measurement function. Variant values are inputs here."""
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"""Constructs inputs to stimulus measurement function. Variant values are inputs here."""
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self.port_error_check(port)
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self.port_error_check(port)
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if port != None:
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if port is not None:
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# For dictionary indexing reasons, the name is formatted differently than the signals
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# For dictionary indexing reasons, the name is formatted differently than the signals
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meas_name = "{}{}".format(self.name, port)
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meas_name = "{}{}".format(self.name, port)
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trig_name = self.trig_name_no_port.format(port)
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trig_name = self.trig_name_no_port.format(port)
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@ -203,7 +205,7 @@ class voltage_at_measure(spice_measurement):
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def get_measure_values(self, time_at, port=None):
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def get_measure_values(self, time_at, port=None):
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"""Constructs inputs to stimulus measurement function. Variant values are inputs here."""
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"""Constructs inputs to stimulus measurement function. Variant values are inputs here."""
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self.port_error_check(port)
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self.port_error_check(port)
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if port != None:
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if port is not None:
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# For dictionary indexing reasons, the name is formatted differently than the signals
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# For dictionary indexing reasons, the name is formatted differently than the signals
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meas_name = "{}{}".format(self.name, port)
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meas_name = "{}{}".format(self.name, port)
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targ_name = self.targ_name_no_port.format(port)
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targ_name = self.targ_name_no_port.format(port)
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@ -516,9 +516,9 @@ class simulation():
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self.sen_name = sen_with_port
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self.sen_name = sen_with_port
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debug.warning("Error occurred while determining SEN name. Can cause faults in simulation.")
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debug.warning("Error occurred while determining SEN name. Can cause faults in simulation.")
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column_addr = self.get_column_addr()
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# column_addr = self.get_column_addr()
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bl_name_port, br_name_port = self.get_bl_name(self.graph.all_paths, port)
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bl_name_port, br_name_port = self.get_bl_name(self.graph.all_paths, port)
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port_pos = -1 - len(str(column_addr)) - len(str(port))
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# port_pos = -1 - len(str(column_addr)) - len(str(port))
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if bl_name_port.endswith(str(port) + "_" + str(self.bitline_column)): # single port SRAM case, bl will not be numbered eg bl_0
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if bl_name_port.endswith(str(port) + "_" + str(self.bitline_column)): # single port SRAM case, bl will not be numbered eg bl_0
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self.bl_name = bl_name_port
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self.bl_name = bl_name_port
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