Code formatting

This commit is contained in:
Bugra Onal 2022-09-01 16:19:14 -07:00
parent 05ab45f39b
commit fcfb9391f6
4 changed files with 51 additions and 51 deletions

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@ -605,8 +605,8 @@ class delay(simulation):
return net return net
original_net = net original_net = net
net = net[len(prefix):] net = net[len(prefix):]
net = net.replace(".", "_").replace("[", "\[").replace("]", "\]") net = net.replace(".", "_").replace("[", r"\[").replace("]", r"\]")
for pattern in ["\sN_{}_[MXmx]\S+_[gsd]".format(net), net]: for pattern in [r"\sN_{}_[MXmx]\S+_[gsd]".format(net), net]:
try: try:
match = check_output(["grep", "-m1", "-o", "-iE", pattern, self.sp_file]) match = check_output(["grep", "-m1", "-o", "-iE", pattern, self.sp_file])
return prefix + match.decode().strip() return prefix + match.decode().strip()
@ -616,8 +616,8 @@ class delay(simulation):
def load_all_measure_nets(self): def load_all_measure_nets(self):
measurement_nets = set() measurement_nets = set()
for port, meas in zip(self.targ_read_ports * len(self.read_meas_lists) + for port, meas in zip(self.targ_read_ports * len(self.read_meas_lists)
self.targ_write_ports * len(self.write_meas_lists), + self.targ_write_ports * len(self.write_meas_lists),
self.read_meas_lists + self.write_meas_lists): self.read_meas_lists + self.write_meas_lists):
for measurement in meas: for measurement in meas:
visited = getattr(measurement, 'pex_visited', False) visited = getattr(measurement, 'pex_visited', False)
@ -1168,7 +1168,7 @@ class delay(simulation):
# 4) At the minimum period, measure the delay, slew and power for all slew/load pairs. # 4) At the minimum period, measure the delay, slew and power for all slew/load pairs.
self.period = min_period self.period = min_period
char_port_data = self.simulate_loads_and_slews(load_slews, leakage_offset) char_port_data = self.simulate_loads_and_slews(load_slews, leakage_offset)
if OPTS.use_specified_load_slew != None and len(load_slews) > 1: if OPTS.use_specified_load_slew is not None and len(load_slews) > 1:
debug.warning("Path delay lists not correctly generated for characterizations of more than 1 load,slew") debug.warning("Path delay lists not correctly generated for characterizations of more than 1 load,slew")
# Get and save the path delays # Get and save the path delays
bl_names, bl_delays, sen_names, sen_delays = self.get_delay_lists(self.path_delays) bl_names, bl_delays, sen_names, sen_delays = self.get_delay_lists(self.path_delays)
@ -1194,7 +1194,6 @@ class delay(simulation):
"""Simulate all specified output loads and input slews pairs of all ports""" """Simulate all specified output loads and input slews pairs of all ports"""
measure_data = self.get_empty_measure_data_dict() measure_data = self.get_empty_measure_data_dict()
path_dict = {}
# Set the target simulation ports to all available ports. This make sims slower but failed sims exit anyways. # Set the target simulation ports to all available ports. This make sims slower but failed sims exit anyways.
self.targ_read_ports = self.read_ports self.targ_read_ports = self.read_ports
self.targ_write_ports = self.write_ports self.targ_write_ports = self.write_ports
@ -1352,9 +1351,9 @@ class delay(simulation):
# Get any available read/write port in case only a single write or read ports is being characterized. # Get any available read/write port in case only a single write or read ports is being characterized.
cur_read_port = self.get_available_port(get_read_port=True) cur_read_port = self.get_available_port(get_read_port=True)
cur_write_port = self.get_available_port(get_read_port=False) cur_write_port = self.get_available_port(get_read_port=False)
debug.check(cur_read_port != None, debug.check(cur_read_port is not None,
"Characterizer requires at least 1 read port") "Characterizer requires at least 1 read port")
debug.check(cur_write_port != None, debug.check(cur_write_port is not None,
"Characterizer requires at least 1 write port") "Characterizer requires at least 1 write port")
# Create test cycles for specified target ports. # Create test cycles for specified target ports.

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@ -146,7 +146,6 @@ class functional(simulation):
comment = self.gen_cycle_comment("noop", "0" * self.word_size, "0" * self.addr_size, "0" * self.num_wmasks, 0, self.t_current) comment = self.gen_cycle_comment("noop", "0" * self.word_size, "0" * self.addr_size, "0" * self.num_wmasks, 0, self.t_current)
self.add_noop_all_ports(comment) self.add_noop_all_ports(comment)
# 1. Write all the write ports 2x to seed a bunch of locations. # 1. Write all the write ports 2x to seed a bunch of locations.
for i in range(3): for i in range(3):
for port in self.write_ports: for port in self.write_ports:

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@ -11,6 +11,7 @@ from abc import ABC, abstractmethod
from .stimuli import * from .stimuli import *
from .charutils import * from .charutils import *
class spice_measurement(ABC): class spice_measurement(ABC):
"""Base class for spice stimulus measurements.""" """Base class for spice stimulus measurements."""
def __init__(self, measure_name, measure_scale=None, has_port=True): def __init__(self, measure_name, measure_scale=None, has_port=True):
@ -21,6 +22,7 @@ class spice_measurement(ABC):
# Some meta values used externally. variables are added here for consistency accross the objects # Some meta values used externally. variables are added here for consistency accross the objects
self.meta_str = None self.meta_str = None
self.meta_add_delay = False self.meta_add_delay = False
@abstractmethod @abstractmethod
def get_measure_function(self): def get_measure_function(self):
return None return None
@ -31,26 +33,26 @@ class spice_measurement(ABC):
def write_measure(self, stim_obj, input_tuple): def write_measure(self, stim_obj, input_tuple):
measure_func = self.get_measure_function() measure_func = self.get_measure_function()
if measure_func == None: if measure_func is None:
debug.error("Did not set measure function", 1) debug.error("Did not set measure function", 1)
measure_vals = self.get_measure_values(*input_tuple) measure_vals = self.get_measure_values(*input_tuple)
measure_func(stim_obj, *measure_vals) measure_func(stim_obj, *measure_vals)
def retrieve_measure(self, port=None): def retrieve_measure(self, port=None):
self.port_error_check(port) self.port_error_check(port)
if port != None: if port is not None:
value = parse_spice_list("timing", "{0}{1}".format(self.name.lower(), port)) value = parse_spice_list("timing", "{0}{1}".format(self.name.lower(), port))
else: else:
value = parse_spice_list("timing", "{0}".format(self.name.lower())) value = parse_spice_list("timing", "{0}".format(self.name.lower()))
if type(value)!=float or self.measure_scale == None: if type(value)!=float or self.measure_scale is None:
return value return value
else: else:
return value * self.measure_scale return value * self.measure_scale
def port_error_check(self, port): def port_error_check(self, port):
if self.has_port and port == None: if self.has_port and port is None:
debug.error("Cannot retrieve measurement, port input was expected.", 1) debug.error("Cannot retrieve measurement, port input was expected.", 1)
elif not self.has_port and port != None: elif not self.has_port and port is not None:
debug.error("Unexpected port input received during measure retrieval.", 1) debug.error("Unexpected port input received during measure retrieval.", 1)
@ -90,7 +92,7 @@ class delay_measure(spice_measurement):
trig_val = self.trig_val_of_vdd * vdd_voltage trig_val = self.trig_val_of_vdd * vdd_voltage
targ_val = self.targ_val_of_vdd * vdd_voltage targ_val = self.targ_val_of_vdd * vdd_voltage
if port != None: if port is not None:
# For dictionary indexing reasons, the name is formatted differently than the signals # For dictionary indexing reasons, the name is formatted differently than the signals
meas_name = "{}{}".format(self.name, port) meas_name = "{}{}".format(self.name, port)
trig_name = self.trig_name_no_port.format(port) trig_name = self.trig_name_no_port.format(port)
@ -145,7 +147,7 @@ class power_measure(spice_measurement):
def get_measure_values(self, t_initial, t_final, port=None): def get_measure_values(self, t_initial, t_final, port=None):
"""Constructs inputs to stimulus measurement function. Variant values are inputs here.""" """Constructs inputs to stimulus measurement function. Variant values are inputs here."""
self.port_error_check(port) self.port_error_check(port)
if port != None: if port is not None:
meas_name = "{}{}".format(self.name, port) meas_name = "{}{}".format(self.name, port)
else: else:
meas_name = self.name meas_name = self.name
@ -172,7 +174,7 @@ class voltage_when_measure(spice_measurement):
def get_measure_values(self, trig_td, vdd_voltage, port=None): def get_measure_values(self, trig_td, vdd_voltage, port=None):
"""Constructs inputs to stimulus measurement function. Variant values are inputs here.""" """Constructs inputs to stimulus measurement function. Variant values are inputs here."""
self.port_error_check(port) self.port_error_check(port)
if port != None: if port is not None:
# For dictionary indexing reasons, the name is formatted differently than the signals # For dictionary indexing reasons, the name is formatted differently than the signals
meas_name = "{}{}".format(self.name, port) meas_name = "{}{}".format(self.name, port)
trig_name = self.trig_name_no_port.format(port) trig_name = self.trig_name_no_port.format(port)
@ -203,7 +205,7 @@ class voltage_at_measure(spice_measurement):
def get_measure_values(self, time_at, port=None): def get_measure_values(self, time_at, port=None):
"""Constructs inputs to stimulus measurement function. Variant values are inputs here.""" """Constructs inputs to stimulus measurement function. Variant values are inputs here."""
self.port_error_check(port) self.port_error_check(port)
if port != None: if port is not None:
# For dictionary indexing reasons, the name is formatted differently than the signals # For dictionary indexing reasons, the name is formatted differently than the signals
meas_name = "{}{}".format(self.name, port) meas_name = "{}{}".format(self.name, port)
targ_name = self.targ_name_no_port.format(port) targ_name = self.targ_name_no_port.format(port)

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@ -516,9 +516,9 @@ class simulation():
self.sen_name = sen_with_port self.sen_name = sen_with_port
debug.warning("Error occurred while determining SEN name. Can cause faults in simulation.") debug.warning("Error occurred while determining SEN name. Can cause faults in simulation.")
column_addr = self.get_column_addr() # column_addr = self.get_column_addr()
bl_name_port, br_name_port = self.get_bl_name(self.graph.all_paths, port) bl_name_port, br_name_port = self.get_bl_name(self.graph.all_paths, port)
port_pos = -1 - len(str(column_addr)) - len(str(port)) # port_pos = -1 - len(str(column_addr)) - len(str(port))
if bl_name_port.endswith(str(port) + "_" + str(self.bitline_column)): # single port SRAM case, bl will not be numbered eg bl_0 if bl_name_port.endswith(str(port) + "_" + str(self.bitline_column)): # single port SRAM case, bl will not be numbered eg bl_0
self.bl_name = bl_name_port self.bl_name = bl_name_port