mirror of https://github.com/VLSIDA/OpenRAM.git
Add via when write driver supply is different layer
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03e0c14ab2
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@ -117,9 +117,10 @@ class write_mask_and_array(design.design):
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for i in range(self.num_wmasks):
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for i in range(self.num_wmasks):
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# Route the A pin over to the left so that it doesn't conflict with the sense
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# Route the A pin over to the left so that it doesn't conflict with the sense
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# amp output which is usually in the center
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# amp output which is usually in the center
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a_pin = self.and2_insts[i].get_pin("A")
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inst = self.and2_insts[i]
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a_pin = inst.get_pin("A")
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a_pos = a_pin.center()
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a_pos = a_pin.center()
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in_pos = vector(self.and2_insts[i].lx(),
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in_pos = vector(inst.lx(),
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a_pos.y)
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a_pos.y)
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self.add_via_stack_center(from_layer=a_pin.layer,
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self.add_via_stack_center(from_layer=a_pin.layer,
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to_layer="m2",
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to_layer="m2",
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@ -130,15 +131,22 @@ class write_mask_and_array(design.design):
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self.add_path(a_pin.layer, [in_pos, a_pos])
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self.add_path(a_pin.layer, [in_pos, a_pos])
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# Copy remaining layout pins
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# Copy remaining layout pins
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self.copy_layout_pin(self.and2_insts[i], "Z", "wmask_out_{0}".format(i))
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self.copy_layout_pin(inst, "Z", "wmask_out_{0}".format(i))
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# Add via connections to metal3 for AND array's B pin
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# Add via connections to metal3 for AND array's B pin
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en_pin = self.and2_insts[i].get_pin("B")
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en_pin = inst.get_pin("B")
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en_pos = en_pin.center()
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en_pos = en_pin.center()
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self.add_via_stack_center(from_layer=en_pin.layer,
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self.add_via_stack_center(from_layer=en_pin.layer,
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to_layer="m3",
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to_layer="m3",
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offset=en_pos)
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offset=en_pos)
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# Add connection to the supply
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for supply_name in ["gnd", "vdd"]:
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supply_pin = inst.get_pin(supply_name)
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self.add_via_stack_center(from_layer=supply_pin.layer,
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to_layer="m1",
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offset=supply_pin.center())
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for supply in ["gnd", "vdd"]:
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for supply in ["gnd", "vdd"]:
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supply_pin = self.and2_insts[0].get_pin(supply)
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supply_pin = self.and2_insts[0].get_pin(supply)
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supply_pin_yoffset = supply_pin.cy()
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supply_pin_yoffset = supply_pin.cy()
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