Made all cin function relate to farads and all input_load relate to relative units.

compiler/modules/sense_amp.py

@@ -33,7 +33,10 @@ class sense_amp(design.design):
         self.pin_map = sense_amp.pin_map
         self.add_pin_types(self.type_list)
         
-    def input_load(self):
+    def get_cin(self):
+    
+        # FIXME: This input load will be applied to both the s_en timing and bitline timing.
+        
         #Input load for the bitlines which are connected to the source/drain of a TX. Not the selects.
         from tech import spice, parameter
         # Default is 8x. Per Samira and Hodges-Jackson book:

compiler/modules/tri_gate.py

@@ -12,7 +12,7 @@ from tech import GDS,layer
 
 class tri_gate(design.design):
     """
-    This module implements the tri gate cell used in the design for
+    This module implements the tri gate cell used in the design forS
     bit-line isolation. It is a hand-made cell, so the layout and
     netlist should be available in the technology library.  
     """
@@ -42,7 +42,7 @@ class tri_gate(design.design):
         total_power = self.return_power() 
         return total_power
 
-    def input_load(self):
+    def get_cin(self):
         return 9*spice["min_tx_gate_c"]
 
     def build_graph(self, graph, inst_name, port_nets):