split pbitcell tests

compiler/tests/04_single_level_column_mux_pbitcell_test.py

@@ -0,0 +1,49 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+#@unittest.skip("SKIPPING 04_driver_test")
+
+class single_level_column_mux_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+
+        # check single level column mux in multi-port
+        OPTS.bitcell = "pbitcell"
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 1
+        OPTS.num_w_ports = 1
+
+        factory.reset()
+        debug.info(2, "Checking column mux for pbitcell (innermost connections)")
+        tx = factory.create(module_type="single_level_column_mux", tx_size=8, bitcell_bl="bl0", bitcell_br="br0")
+        self.local_check(tx)
+
+        factory.reset()
+        debug.info(2, "Checking column mux for pbitcell (outermost connections)")
+        tx = factory.create(module_type="single_level_column_mux",tx_size=8, bitcell_bl="bl2", bitcell_br="br2")
+        self.local_check(tx)
+
+        globals.end_openram()
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/04_single_level_column_mux_test.py

@@ -28,22 +28,6 @@ class single_level_column_mux_test(openram_test):
         tx = factory.create(module_type="single_level_column_mux", tx_size=8)
         self.local_check(tx)
 
-        # check single level column mux in multi-port
-        OPTS.bitcell = "pbitcell"
-        OPTS.num_rw_ports = 1
-        OPTS.num_r_ports = 1
-        OPTS.num_w_ports = 1
-
-        factory.reset()
-        debug.info(2, "Checking column mux for pbitcell (innermost connections)")
-        tx = factory.create(module_type="single_level_column_mux", tx_size=8, bitcell_bl="bl0", bitcell_br="br0")
-        self.local_check(tx)
-        
-        factory.reset()
-        debug.info(2, "Checking column mux for pbitcell (outermost connections)")
-        tx = factory.create(module_type="single_level_column_mux",tx_size=8, bitcell_bl="bl2", bitcell_br="br2")
-        self.local_check(tx)
-
         globals.end_openram()
 
 # run the test from the command line

compiler/tests/07_single_level_column_mux_array_pbitcell_test.py

@@ -0,0 +1,55 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+class single_level_column_mux_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+        import single_level_column_mux_array
+
+        # check single level column mux array in multi-port
+        OPTS.bitcell = "pbitcell"
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 1
+        OPTS.num_w_ports = 1
+
+        factory.reset()
+        debug.info(1, "Testing sample for 2-way column_mux_array in multi-port")
+        a = factory.create(module_type="single_level_column_mux_array", columns=16, word_size=8, bitcell_bl="bl0", bitcell_br="br0")
+        self.local_check(a)
+
+        debug.info(1, "Testing sample for 4-way column_mux_array  in multi-port")
+        a = factory.create(module_type="single_level_column_mux_array", columns=16, word_size=4, bitcell_bl="bl0", bitcell_br="br0")
+        self.local_check(a)
+
+        debug.info(1, "Testing sample for 8-way column_mux_array  in multi-port (innermost connections)")
+        a = factory.create(module_type="single_level_column_mux_array", columns=32, word_size=4, bitcell_bl="bl0", bitcell_br="br0")
+        self.local_check(a)
+
+        debug.info(1, "Testing sample for 8-way column_mux_array  in multi-port (outermost connections)")
+        a = factory.create(module_type="single_level_column_mux_array", columns=32, word_size=4, bitcell_bl="bl2", bitcell_br="br2")
+        self.local_check(a)
+
+        globals.end_openram()
+
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/07_single_level_column_mux_array_test.py

@@ -34,29 +34,6 @@ class single_level_column_mux_test(openram_test):
         a = factory.create(module_type="single_level_column_mux_array", columns=32, word_size=4)
         self.local_check(a)
 
-        # check single level column mux array in multi-port
-        OPTS.bitcell = "pbitcell"
-        OPTS.num_rw_ports = 1
-        OPTS.num_r_ports = 1
-        OPTS.num_w_ports = 1
-
-        factory.reset()
-        debug.info(1, "Testing sample for 2-way column_mux_array in multi-port")
-        a = factory.create(module_type="single_level_column_mux_array", columns=16, word_size=8, bitcell_bl="bl0", bitcell_br="br0")
-        self.local_check(a)
-
-        debug.info(1, "Testing sample for 4-way column_mux_array  in multi-port")
-        a = factory.create(module_type="single_level_column_mux_array", columns=16, word_size=4, bitcell_bl="bl0", bitcell_br="br0")
-        self.local_check(a)
-
-        debug.info(1, "Testing sample for 8-way column_mux_array  in multi-port (innermost connections)")
-        a = factory.create(module_type="single_level_column_mux_array", columns=32, word_size=4, bitcell_bl="bl0", bitcell_br="br0")
-        self.local_check(a)
-        
-        debug.info(1, "Testing sample for 8-way column_mux_array  in multi-port (outermost connections)")
-        a = factory.create(module_type="single_level_column_mux_array", columns=32, word_size=4, bitcell_bl="bl2", bitcell_br="br2")
-        self.local_check(a)
-
         globals.end_openram()
 
 

compiler/tests/08_wordline_driver_pbitcell_test.py

@@ -0,0 +1,44 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+#@unittest.skip("SKIPPING 04_driver_test")
+
+class wordline_driver_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+
+        # check wordline driver for multi-port
+        OPTS.bitcell = "pbitcell"
+        OPTS.num_rw_ports = 1
+        OPTS.num_w_ports = 0
+        OPTS.num_r_ports = 0
+
+        factory.reset()
+        debug.info(2, "Checking driver (multi-port case)")
+        tx = factory.create(module_type="wordline_driver", rows=8, cols=64)
+        self.local_check(tx)
+
+        globals.end_openram()
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/08_wordline_driver_test.py

@@ -28,17 +28,6 @@ class wordline_driver_test(openram_test):
         tx = factory.create(module_type="wordline_driver", rows=8, cols=32)
         self.local_check(tx)
 
-        # check wordline driver for multi-port
-        OPTS.bitcell = "pbitcell"
-        OPTS.num_rw_ports = 1
-        OPTS.num_w_ports = 0
-        OPTS.num_r_ports = 0
-
-        factory.reset()
-        debug.info(2, "Checking driver (multi-port case)")
-        tx = factory.create(module_type="wordline_driver", rows=8, cols=64)
-        self.local_check(tx)
-
         globals.end_openram()
 
 # run the test from the command line

compiler/tests/09_sense_amp_array_test.py

@@ -34,21 +34,6 @@ class sense_amp_test(openram_test):
         a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=4)
         self.local_check(a)
 
-        # check sense amp array for multi-port
-        OPTS.bitcell = "pbitcell"
-        OPTS.num_rw_ports = 1
-        OPTS.num_w_ports = 0
-        OPTS.num_r_ports = 0
-
-        factory.reset()
-        debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2 (multi-port case)")
-        a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=2)
-        self.local_check(a)
-
-        debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=4 (multi-port case)")
-        a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=4)
-        self.local_check(a)
-
         globals.end_openram()
 
 # run the test from the command line

compiler/tests/09_sense_amp_array_test_pbitcell.py

@@ -0,0 +1,46 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+class sense_amp_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+
+        #check sense amp array for multi-port
+        OPTS.bitcell = "pbitcell"
+        OPTS.num_rw_ports = 1
+        OPTS.num_w_ports = 0
+        OPTS.num_r_ports = 0
+
+        factory.reset()
+        debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2 (multi-port case)")
+        a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=2)
+        self.local_check(a)
+
+        debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=4 (multi-port case)")
+        a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=4)
+        self.local_check(a)
+
+        globals.end_openram()
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/10_write_driver_array_pbitcell_test.py

@@ -0,0 +1,46 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+class write_driver_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+
+        # check write driver array for multi-port
+        OPTS.bitcell = "pbitcell"
+        OPTS.num_rw_ports = 1
+        OPTS.num_w_ports = 0
+        OPTS.num_r_ports = 0
+
+        factory.reset()
+        debug.info(2, "Testing write_driver_array for columns=8, word_size=8 (multi-port case)")
+        a = factory.create(module_type="write_driver_array", columns=8, word_size=8)
+        self.local_check(a)
+
+        debug.info(2, "Testing write_driver_array for columns=16, word_size=8 (multi-port case)")
+        a = factory.create(module_type="write_driver_array", columns=16, word_size=8)
+        self.local_check(a)
+
+        globals.end_openram()
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/10_write_driver_array_test.py

@@ -30,21 +30,6 @@ class write_driver_test(openram_test):
         a = factory.create(module_type="write_driver_array", columns=16, word_size=8)
         self.local_check(a)
 
-        # check write driver array for multi-port
-        OPTS.bitcell = "pbitcell"
-        OPTS.num_rw_ports = 1
-        OPTS.num_w_ports = 0
-        OPTS.num_r_ports = 0
-
-        factory.reset()
-        debug.info(2, "Testing write_driver_array for columns=8, word_size=8 (multi-port case)")
-        a = factory.create(module_type="write_driver_array", columns=8, word_size=8)
-        self.local_check(a)
-
-        debug.info(2, "Testing write_driver_array for columns=16, word_size=8 (multi-port case)")
-        a = factory.create(module_type="write_driver_array", columns=16, word_size=8)
-        self.local_check(a)
-        
         globals.end_openram()
 
 # run the test from the command line

compiler/tests/10_write_driver_array_wmask_pbitcell_test.py

@@ -0,0 +1,49 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys, os
+
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+
+class write_driver_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+
+        # check write driver array for multi-port
+        OPTS.bitcell = "pbitcell"
+        OPTS.num_rw_ports = 1
+        OPTS.num_w_ports = 0
+        OPTS.num_r_ports = 0
+
+        factory.reset()
+        debug.info(2, "Testing write_driver_array for columns=8, word_size=8, write_size=4 (multi-port case)")
+        a = factory.create(module_type="write_driver_array", columns=8, word_size=8, write_size=4)
+        self.local_check(a)
+
+        debug.info(2, "Testing write_driver_array for columns=16, word_size=8, write_size=4 (multi-port case)")
+        a = factory.create(module_type="write_driver_array", columns=16, word_size=8, write_size=4)
+        self.local_check(a)
+
+        globals.end_openram()
+
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/10_write_driver_array_wmask_test.py

@@ -36,21 +36,6 @@ class write_driver_test(openram_test):
         a = factory.create(module_type="write_driver_array", columns=16, word_size=8, write_size=4)
         self.local_check(a)
 
-        # check write driver array for multi-port
-        OPTS.bitcell = "pbitcell"
-        OPTS.num_rw_ports = 1
-        OPTS.num_w_ports = 0
-        OPTS.num_r_ports = 0
-
-        factory.reset()
-        debug.info(2, "Testing write_driver_array for columns=8, word_size=8, write_size=4 (multi-port case)")
-        a = factory.create(module_type="write_driver_array", columns=8, word_size=8, write_size=4)
-        self.local_check(a)
-
-        debug.info(2, "Testing write_driver_array for columns=16, word_size=8, write_size=4 (multi-port case)")
-        a = factory.create(module_type="write_driver_array", columns=16, word_size=8, write_size=4)
-        self.local_check(a)
-
         globals.end_openram()
 
 

compiler/tests/10_write_mask_and_array_pbitcell_test.py

@@ -0,0 +1,49 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys, os
+
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+
+class write_mask_and_array_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+
+        # check write driver array for multi-port
+        OPTS.bitcell = "pbitcell"
+        OPTS.num_rw_ports = 1
+        OPTS.num_w_ports = 0
+        OPTS.num_r_ports = 0
+
+        factory.reset()
+        debug.info(2, "Testing write_mask_and_array for columns=8, word_size=8, write_size=4 (multi-port case)")
+        a = factory.create(module_type="write_mask_and_array", columns=8, word_size=8, write_size=4)
+        self.local_check(a)
+
+        debug.info(2, "Testing write_mask_and_array for columns=16, word_size=8, write_size=2 (multi-port case)")
+        a = factory.create(module_type="write_mask_and_array", columns=16, word_size=8, write_size=2)
+        self.local_check(a)
+
+        globals.end_openram()
+
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/10_write_mask_and_array_test.py

@@ -36,21 +36,6 @@ class write_mask_and_array_test(openram_test):
         a = factory.create(module_type="write_mask_and_array", columns=16, word_size=8, write_size=2)
         self.local_check(a)
 
-        # check write driver array for multi-port
-        OPTS.bitcell = "pbitcell"
-        OPTS.num_rw_ports = 1
-        OPTS.num_w_ports = 0
-        OPTS.num_r_ports = 0
-
-        factory.reset()
-        debug.info(2, "Testing write_mask_and_array for columns=8, word_size=8, write_size=4 (multi-port case)")
-        a = factory.create(module_type="write_mask_and_array", columns=8, word_size=8, write_size=4)
-        self.local_check(a)
-
-        debug.info(2, "Testing write_mask_and_array for columns=16, word_size=8, write_size=2 (multi-port case)")
-        a = factory.create(module_type="write_mask_and_array", columns=16, word_size=8, write_size=2)
-        self.local_check(a)
-
         globals.end_openram()
 
 

compiler/tests/19_bank_select_pbitcell_test.py

@@ -0,0 +1,48 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+class bank_select_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+
+        OPTS.bitcell = "pbitcell"
+        debug.info(1, "No column mux, rw control logic")
+        a = factory.create(module_type="bank_select", port="rw")
+        self.local_check(a)
+
+        OPTS.num_rw_ports = 0
+        OPTS.num_w_ports = 1
+        OPTS.num_r_ports = 1
+
+        debug.info(1, "No column mux, w control logic")
+        a = factory.create(module_type="bank_select", port="w")
+        self.local_check(a)
+
+        debug.info(1, "No column mux, r control logic")
+        a = factory.create(module_type="bank_select", port="r")
+        self.local_check(a)
+
+        globals.end_openram()
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/19_bank_select_test.py

@@ -25,23 +25,6 @@ class bank_select_test(openram_test):
         a = factory.create(module_type="bank_select", port="rw")
         self.local_check(a)
 
-        OPTS.bitcell = "pbitcell"
-        debug.info(1, "No column mux, rw control logic")
-        a = factory.create(module_type="bank_select", port="rw")
-        self.local_check(a)
-        
-        OPTS.num_rw_ports = 0
-        OPTS.num_w_ports = 1
-        OPTS.num_r_ports = 1
-
-        debug.info(1, "No column mux, w control logic")
-        a = factory.create(module_type="bank_select", port="w")
-        self.local_check(a)
-        
-        debug.info(1, "No column mux, r control logic")
-        a = factory.create(module_type="bank_select", port="r")
-        self.local_check(a)
-        
         globals.end_openram()
 
 # run the test from the command line