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split pbitcell tests

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This commit is contained in:
Joey Kunzler
2020-04-17 12:26:18 -07:00
parent f1925420cf
commit fbc6dfdaac
20 changed files with 398 additions and 139 deletions
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compiler/tests/10_write_driver_array_test.py
-15
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@@ -29,22 +29,7 @@ class write_driver_test(openram_test):
debug.info(2, "Testing write_driver_array for columns=16, word_size=8")
a = factory.create(module_type="write_driver_array", columns=16, word_size=8)
self.local_check(a)
# check write driver array for multi-port
OPTS.bitcell = "pbitcell"
OPTS.num_rw_ports = 1
OPTS.num_w_ports = 0
OPTS.num_r_ports = 0
factory.reset()
debug.info(2, "Testing write_driver_array for columns=8, word_size=8 (multi-port case)")
a = factory.create(module_type="write_driver_array", columns=8, word_size=8)
self.local_check(a)
debug.info(2, "Testing write_driver_array for columns=16, word_size=8 (multi-port case)")
a = factory.create(module_type="write_driver_array", columns=16, word_size=8)
self.local_check(a)
globals.end_openram()
# run the test from the command line