mirror of https://github.com/VLSIDA/OpenRAM.git
Fix missing include
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parent
d209e8d9a3
commit
fb9956fe96
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@ -8,6 +8,7 @@
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import debug
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import debug
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import bitcell_base
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import bitcell_base
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from tech import cell_properties as props
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from tech import cell_properties as props
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from tech import parameter
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class replica_bitcell(bitcell_base.bitcell_base):
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class replica_bitcell(bitcell_base.bitcell_base):
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@ -8,6 +8,7 @@
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import debug
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import debug
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import bitcell_base
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import bitcell_base
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from tech import cell_properties as props
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from tech import cell_properties as props
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from tech import parameter
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class replica_bitcell_1rw_1r(bitcell_base.bitcell_base):
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class replica_bitcell_1rw_1r(bitcell_base.bitcell_base):
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