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Fix pin nameon sense amp spice. Fix NAND2 bug in hierarchical decoder.

This commit is contained in:
Matt Guthaus 2018-02-02 14:08:56 -08:00
parent 3be59fb762
commit fb90b8f5fe
5 changed files with 17 additions and 13 deletions
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4
compiler/hierarchical_predecode.py
View File

@ -250,9 +250,9 @@ class hierarchical_predecode(design.design):
index_lst= nand_input_line_combination[k]
if self.number_of_inputs == 2:
gate_lst = ["B","A"]
gate_lst = ["A","B"]
else:
gate_lst = ["C","B","A"]
gate_lst = ["A","B","C"]
# this will connect pins A,B or A,B,C
for rail_pin,gate_pin in zip(index_lst,gate_lst):

6
compiler/hierarchical_predecode2x4.py
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@ -27,10 +27,10 @@ class hierarchical_predecode2x4(hierarchical_predecode):
self.create_rails()
self.add_input_inverters()
self.add_output_inverters()
connections =[["in[0]", "in[1]", "Z[3]", "vdd", "gnd"],
["inbar[0]", "in[1]", "Z[2]", "vdd", "gnd"],
connections =[["inbar[0]", "inbar[1]", "Z[0]", "vdd", "gnd"],
["in[0]", "inbar[1]", "Z[1]", "vdd", "gnd"],
["inbar[0]", "inbar[1]", "Z[0]", "vdd", "gnd"]]
["inbar[0]", "in[1]", "Z[2]", "vdd", "gnd"],
["in[0]", "in[1]", "Z[3]", "vdd", "gnd"]]
self.add_nand(connections)
self.route()

4
compiler/tests/06_hierarchical_decoder_test.py
View File

@ -32,6 +32,10 @@ class hierarchical_decoder_test(openram_test):
# a = hierarchical_decoder.hierarchical_decoder(rows=8)
# self.local_check(a)
debug.info(1, "Testing 16 row sample for hierarchical_decoder")
a = hierarchical_decoder.hierarchical_decoder(rows=16)
self.local_check(a)
debug.info(1, "Testing 32 row sample for hierarchical_decoder")
a = hierarchical_decoder.hierarchical_decoder(rows=32)
self.local_check(a)

8
technology/freepdk45/sp_lib/sense_amp.sp
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@ -1,11 +1,11 @@
.SUBCKT sense_amp bl br dout sclk vdd gnd
.SUBCKT sense_amp bl br dout en vdd gnd
M_1 dout net_1 vdd vdd pmos_vtg w=540.0n l=50.0n
M_3 net_1 dout vdd vdd pmos_vtg w=540.0n l=50.0n
M_2 dout net_1 net_2 gnd nmos_vtg w=270.0n l=50.0n
M_8 net_1 dout net_2 gnd nmos_vtg w=270.0n l=50.0n
M_5 bl sclk dout vdd pmos_vtg w=720.0n l=50.0n
M_6 br sclk net_1 vdd pmos_vtg w=720.0n l=50.0n
M_7 net_2 sclk gnd gnd nmos_vtg w=270.0n l=50.0n
M_5 bl en dout vdd pmos_vtg w=720.0n l=50.0n
M_6 br en net_1 vdd pmos_vtg w=720.0n l=50.0n
M_7 net_2 en gnd gnd nmos_vtg w=270.0n l=50.0n
.ENDS sense_amp

8
technology/scn3me_subm/sp_lib/sense_amp.sp
View File

@ -1,12 +1,12 @@
*********************** "sense_amp" ******************************
.SUBCKT sense_amp bl br dout sclk vdd gnd
.SUBCKT sense_amp bl br dout en vdd gnd
M_1 dout net_1 vdd vdd p W='5.4*1u' L=0.6u
M_2 dout net_1 net_2 gnd n W='2.7*1u' L=0.6u
M_3 net_1 dout vdd vdd p W='5.4*1u' L=0.6u
M_4 net_1 dout net_2 gnd n W='2.7*1u' L=0.6u
M_5 bl sclk dout vdd p W='7.2*1u' L=0.6u
M_6 br sclk net_1 vdd p W='7.2*1u' L=0.6u
M_7 net_2 sclk gnd gnd n W='2.7*1u' L=0.6u
M_5 bl en dout vdd p W='7.2*1u' L=0.6u
M_6 br en net_1 vdd p W='7.2*1u' L=0.6u
M_7 net_2 en gnd gnd n W='2.7*1u' L=0.6u
.ENDS sense_amp