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fix the [0] problem in spare_wen

This commit is contained in:
FriedrichWu 2024-07-15 14:59:25 +02:00
parent 8ecdc939d0
commit fb7f92394b
1 changed files with 60 additions and 24 deletions
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84
compiler/modules/sram_part.py
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@ -80,7 +80,10 @@ class sram_1bank(design, verilog, lef):
for bit in range(self.num_wmasks): for bit in range(self.num_wmasks):
self.add_pin("bank_wmask{0}[{1}]".format(port, bit), "INPUT") self.add_pin("bank_wmask{0}[{1}]".format(port, bit), "INPUT")
for bit in range(self.num_spare_cols): for bit in range(self.num_spare_cols):
self.add_pin("bank_spare_wen{0}[{1}]".format(port, bit), "INPUT") if self.num_spare_cols ==1:
self.add_pin("bank_spare_wen{0}".format(port), "INPUT")
else:
self.add_pin("bank_spare_wen{0}[{1}]".format(port, bit), "INPUT")
for port in self.all_ports: for port in self.all_ports:
self.add_pin("wl_en{0}".format(port), "INPUT") self.add_pin("wl_en{0}".format(port), "INPUT")
@ -204,10 +207,16 @@ class sram_1bank(design, verilog, lef):
# lef file use this pin name, should be same with new pin # lef file use this pin name, should be same with new pin
for port in self.all_ports: for port in self.all_ports:
for bit in range(self.num_spare_cols): for bit in range(self.num_spare_cols):
# input if self.num_spare_cols == 1:
self.add_pin("spare_wen{}[{}]".format(port, bit), "INPUT") # input
# output self.add_pin("spare_wen{}".format(port), "INPUT")
self.add_pin("bank_spare_wen{}[{}]".format(port, bit), "OUTPUT") # output
self.add_pin("bank_spare_wen{}".format(port), "OUTPUT")
else:
# input
self.add_pin("spare_wen{}[{}]".format(port, bit), "INPUT")
# output
self.add_pin("bank_spare_wen{}[{}]".format(port, bit), "OUTPUT")
#clk_buf, regard as input #clk_buf, regard as input
self.add_pin("clk_buf{}".format(port), "INPUT") self.add_pin("clk_buf{}".format(port), "INPUT")
# Standard supply and ground names # Standard supply and ground names
@ -1007,10 +1016,16 @@ class sram_1bank(design, verilog, lef):
port = instance_index port = instance_index
for bit in range(self.num_spare_cols): for bit in range(self.num_spare_cols):
# input if self.num_spare_cols == 1:
pins_to_route.append("spare_wen{}[{}]".format(port, bit)) # input
# output pins_to_route.append("spare_wen{}".format(port))
pins_to_route.append("bank_spare_wen{}[{}]".format(port, bit)) # output
pins_to_route.append("bank_spare_wen{}".format(port))
else:
# input
pins_to_route.append("spare_wen{}[{}]".format(port, bit))
# output
pins_to_route.append("bank_spare_wen{}[{}]".format(port, bit))
#clk_buf, regard as input #clk_buf, regard as input
pins_to_route.append("clk_buf{}".format(port)) pins_to_route.append("clk_buf{}".format(port))
@ -1032,16 +1047,28 @@ class sram_1bank(design, verilog, lef):
pin_layer = self.pwr_grid_layers[0] pin_layer = self.pwr_grid_layers[0]
for bit in range(self.num_spare_cols): for bit in range(self.num_spare_cols):
# input if self.num_spare_cols == 1:
self.add_io_pin(self.spare_wen_dff_insts[port], # input
"din_{}".format(bit), # old name self.add_io_pin(self.spare_wen_dff_insts[port],
"spare_wen{}[{}]".format(port, bit), # new name "din_{}".format(bit), # old name
start_layer=pin_layer) "spare_wen{}".format(port), # new name
# output start_layer=pin_layer)
self.add_io_pin(self.spare_wen_dff_insts[port], # output
"dout_{}".format(port, bit), self.add_io_pin(self.spare_wen_dff_insts[port],
"bank_spare_wen{}[{}]".format(port, bit), "dout_{}".format(bit),
start_layer=pin_layer) "bank_spare_wen{}".format(port),
start_layer=pin_layer)
else:
# input
self.add_io_pin(self.spare_wen_dff_insts[port],
"din_{}".format(bit), # old name
"spare_wen{}[{}]".format(port, bit), # new name
start_layer=pin_layer)
# output
self.add_io_pin(self.spare_wen_dff_insts[port],
"dout_{}".format(bit),
"bank_spare_wen{}[{}]".format(port, bit),
start_layer=pin_layer)
#clk_buf, regard as input #clk_buf, regard as input
self.add_io_pin(self.spare_wen_dff_insts[port], self.add_io_pin(self.spare_wen_dff_insts[port],
"clk", "clk",
@ -1348,7 +1375,10 @@ class sram_1bank(design, verilog, lef):
for bit in range(self.num_wmasks): for bit in range(self.num_wmasks):
pins_to_route.append("bank_wmask{0}[{1}]".format(port, bit)) pins_to_route.append("bank_wmask{0}[{1}]".format(port, bit))
for bit in range(self.num_spare_cols): for bit in range(self.num_spare_cols):
pins_to_route.append("bank_spare_wen{0}[{1}]".format(port, bit)) if self.num_spare_cols == 1:
pins_to_route.append("bank_spare_wen{0}".format(port, bit))
else:
pins_to_route.append("bank_spare_wen{0}[{1}]".format(port, bit))
for port in self.all_ports: for port in self.all_ports:
pins_to_route.append("wl_en{0}".format(port)) pins_to_route.append("wl_en{0}".format(port))
@ -1419,10 +1449,16 @@ class sram_1bank(design, verilog, lef):
"bank_wmask{0}[{1}]".format(port, bit), "bank_wmask{0}[{1}]".format(port, bit),
start_layer=pin_layer) start_layer=pin_layer)
for bit in range(self.num_spare_cols): for bit in range(self.num_spare_cols):
self.add_io_pin(self.bank_inst, if self.num_spare_cols == 1:
"bank_spare_wen{0}_{1}".format(port, bit), self.add_io_pin(self.bank_inst,
"bank_spare_wen{0}[{1}]".format(port, bit), "bank_spare_wen{0}_{1}".format(port, bit),
start_layer=pin_layer) "bank_spare_wen{0}".format(port),
start_layer=pin_layer)
else:
self.add_io_pin(self.bank_inst,
"bank_spare_wen{0}_{1}".format(port, bit),
"bank_spare_wen{0}[{1}]".format(port, bit),
start_layer=pin_layer)
if port in self.all_ports: if port in self.all_ports:
self.add_io_pin(self.bank_inst, self.add_io_pin(self.bank_inst,
"wl_en{0}".format(port), "wl_en{0}".format(port),