removed references to technology name

compiler/base/custom_cell_properties.py

@@ -5,6 +5,7 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+from globals import OPTS
 
 class _pins:
     def __init__(self, pin_dict):
@@ -107,6 +108,10 @@ class _dff_buff_array:
         self.use_custom_ports = use_custom_ports
         self.add_body_contacts = add_body_contacts
 
+class _bitcell_array:
+    def __init__(self, use_custom_cell_arrangement):
+        self.use_custom_cell_arrangement = use_custom_cell_arrangement
+
 class cell_properties():
     """
     This contains meta information about the custom designed cells. For
@@ -134,11 +139,14 @@ class cell_properties():
                                     'bl' : 'bl',
                                     'br' : 'br',
                                     'en' : 'en'})
+
         self._sense_amp = _cell({'bl'   : 'bl',
                                  'br'   : 'br',
                                  'dout' : 'dout',
                                  'en'   : 'en'})
 
+        self._bitcell_array = _bitcell_array(use_custom_cell_arrangement = [])
+
     @property
     def bitcell(self):
         return self._bitcell
@@ -162,3 +170,15 @@ class cell_properties():
     @property
     def sense_amp(self):
         return self._sense_amp
+    
+    @property
+    def bitcell_array(self):
+        return self._bitcell_array
+
+    def use_custom_bitcell_array(self, port_list):
+        use_custom_arrangement = False
+        for ports in port_list:
+            if ports == "{}R_{}W_{}RW".format(OPTS.num_r_ports, OPTS.num_w_ports, OPTS.num_rw_ports):
+                use_custom_arrangement = True
+                break
+        return use_custom_arrangement

compiler/modules/bitcell_array.py

@@ -8,6 +8,7 @@
 from bitcell_base_array import bitcell_base_array
 from s8_corner import s8_corner
 from tech import drc, spice
+from tech import cell_properties as props
 from globals import OPTS
 from sram_factory import factory
 
@@ -46,7 +47,7 @@ class bitcell_array(bitcell_base_array):
 
     def add_modules(self):
         """ Add the modules used in this design """
-        if OPTS.tech_name != "sky130":
+        if not props.use_custom_bitcell_array(props.bitcell_array.use_custom_cell_arrangement):
             self.cell = factory.create(module_type="bitcell")
             self.add_mod(self.cell)
 
@@ -73,7 +74,7 @@ class bitcell_array(bitcell_base_array):
     def create_instances(self):
         """ Create the module instances used in this design """
         self.cell_inst = {}
-        if OPTS.tech_name != "sky130":
+        if not props.use_custom_bitcell_array(props.bitcell_array.use_custom_cell_arrangement):
             for col in range(self.column_size):
                 for row in range(self.row_size):
                     name = "bit_r{0}_c{1}".format(row, col)
@@ -81,44 +82,8 @@ class bitcell_array(bitcell_base_array):
                                                         mod=self.cell)
                     self.connect_inst(self.get_bitcell_pins(row, col))
         else:
-            self.array_layout = []
+            from tech import custom_cell_arrangement
-            alternate_bitcell = 0
+            custom_cell_arrangement(self) 
-            for row in range(0,self.row_size):
-
-                row_layout = []
-                
-                alternate_strap = 1
-                for col in range(0,self.column_size):
-                    if alternate_bitcell == 1:
-                        row_layout.append(self.cell)
-                        self.cell_inst[row, col]=self.add_inst(name="row_{}, col_{}_bitcell".format(row,col),
-                                                        mod=self.cell)
-                        
-                        
-                    else:
-                        row_layout.append(self.cell2)
-                        self.cell_inst[row, col]=self.add_inst(name="row_{}, col_{}_bitcell".format(row,col),
-                                mod=self.cell2)
-                        
-                    self.connect_inst(self.get_bitcell_pins(row, col))
-                    if col != self.column_size-1:
-                        if alternate_strap:
-                            row_layout.append(self.strap2)
-                            self.add_inst(name="row_{}, col_{}_wlstrap".format(row,col),
-                                mod=self.strap2)
-                            alternate_strap = 0
-                        else:
-                            
-                            row_layout.append(self.strap)
-                            self.add_inst(name="row_{}, col_{}_wlstrap".format(row,col),
-                                mod=self.strap)
-                            alternate_strap = 1
-                        self.connect_inst([])
-                if alternate_bitcell == 0:
-                    alternate_bitcell = 1
-                else:
-                    alternate_bitcell = 0
-                self.array_layout.append(row_layout)
 
     def analytical_power(self, corner, load):
         """Power of Bitcell array and bitline in nW."""

compiler/modules/bitcell_base_array.py

@@ -196,7 +196,7 @@ class bitcell_base_array(design.design):
 
     def place_array(self, name_template, row_offset=0):
         # We increase it by a well enclosure so the precharges don't overlap our wells
-        if OPTS.tech_name != "sky130":
+        if not cell_properties.use_custom_bitcell_array(cell_properties.bitcell_array.use_custom_cell_arrangement):
             self.height = self.row_size * self.cell.height
             self.width = self.column_size * self.cell.width
 
@@ -222,18 +222,5 @@ class bitcell_base_array(design.design):
                     yoffset += self.cell.height
                 xoffset += self.cell.width
         else:
-
+            from tech import custom_cell_placement
-            self.height = self.row_size * self.cell.height 
+            custom_cell_placement(self)
-            self.width = self.column_size * self.cell.width + (self.column_size-1) * self.strap.width
-            
-
-            yoffset = 0.0
-
-            for row in range(0, len(self.array_layout)):
-                xoffset = 0.0               
-                for col in range(0, len(self.array_layout[row])):
-                    inst = self.insts[col + row*len(self.array_layout[row])]
-                    inst.place(offset=[xoffset, yoffset])
-                    xoffset += inst.width
-                yoffset += self.cell.height
-